The present invention provides a control method to epitaxial growth monolayer graphene, in which a monolayer graphene is epitaxially grown on a non-polar crystal face at arbitrary angle of a non-polar crystal face SiC substrate, thereby utilizing the non-polar crystal face to manipulate the electrical transport properties of graphene. A monolayer graphene having ballistic transport properties can be epitaxially grown at arbitrary angle of non-polar crystal face SiC substrate by the above-mentioned control method.

A silicon carbide-graphite composite is described, including (i) interior bulk graphite material and (ii) exterior silicon carbide matrix material, wherein the interior bulk graphite material and exterior silicon carbide matrix material inter-penetrate one another at an interfacial region therebetween, and wherein graphite is present in inclusions in the exterior silicon carbide matrix material. Such material may be formed by contacting a precursor graphite article with silicon monoxide (SiO) gas under chemical reaction conditions that are effective to convert an exterior portion of the precursor graphite article to a silicon carbide matrix material in which graphite is present in inclusions therein, and wherein the silicon carbide matrix material and interior bulk graphite material interpenetrate one another at an interfacial region therebetween. Such silicon carbide-graphite composite is usefully employed in applications such as implant hard masks in manufacturing solar cells or other optical, optoelectronic, photonic, semiconductor and microelectronic products, as well as in ion implantation system materials, components, and assemblies, such as beam line assemblies, beam steering lenses, ionization chamber liners, beam stops, and ion source chambers.

A voltage tunable solar-blind UV detector using a EG/SiC heterojunction based Schottky emitter bipolar phototransistor with EG grown on p-SiC epi-layer using a chemically accelerated selective etching process of Si using TFS precursor.

A silicon carbide-graphite composite is described, including (i) interior bulk graphite material and (ii) exterior silicon carbide matrix material, wherein the interior bulk graphite material and exterior silicon carbide matrix material inter-penetrate one another at an interfacial region therebetween, and wherein graphite is present in inclusions in the exterior silicon carbide matrix material. Such material may be formed by contacting a precursor graphite article with silicon monoxide (SiO) gas under chemical reaction conditions that are effective to convert an exterior portion of the precursor graphite article to a silicon carbide matrix material in which graphite is present in inclusions therein, and wherein the silicon carbide matrix material and interior bulk graphite material interpenetrate one another at an interfacial region therebetween. Such silicon carbide-graphite composite is usefully employed in applications such as implant hard masks in manufacturing solar cells or other optical, optoelectronic, photonic, semiconductor and microelectronic products, as well as in ion implantation system materials, components, and assemblies, such as beam line assemblies, beam steering lenses, ionization chamber liners, beam stops, and ion source chambers.

Process for manufacturing a 3C-SiC layer, comprising the steps of: providing a wafer of 4H-SiC, provided with a surface; heating, through a LASER beam, a selective portion of the wafer at least up to a melting temperature of the material of the selective portion; allowing the cooling and crystallization of the melted selective portion, thus forming the 3C-SiC layer, a Silicon layer on the 3C-SiC layer and a carbon-rich layer above the Silicon layer; completely removing the carbon-rich layer and the Silicon layer, exposing the 3C-SiC layer. If the Silicon layer is maintained on the 4H-SiC wafer, the process leads to the formation of a Silicon layer on the 4H-SiC wafer. The 3C-SiC or Silicon layer thus formed may be used for the integration, even only partial, of electrical or electronic components.

A method of forming a semiconductor device and a semiconductor device are provided. The method includes forming a graphene layer at a first side of a silicon carbide substrate having at least next to the first side a first defect density of at most 5*10.sup.2/cm.sup.2; attaching an acceptor layer at the graphene layer to form a wafer-stack, the acceptor layer comprising silicon carbide having a second defect density higher than the first defect density; forming an epitaxial silicon carbide layer; splitting the wafer-stack along a split plane in the silicon carbide substrate to form a device wafer comprising the graphene layer and a silicon carbide split layer at the graphene layer; and further processing the device wafer at the upper side.

A layered heterostructure, comprising alternating layers of different semiconductors, wherein one of the atom species of one of the semiconductors has a faster diffusion rate along an oxidizing interface than an atom species of the other semiconductor at an oxidizing temperature, can be used to fabricate embedded nanostructures with arbitrary shape. The result of the oxidation will be an embedded nanostructure comprising the semiconductor having slower diffusing atom species surrounded by the semiconductor having the higher diffusing atom species. The method enables the fabrication of low- and multi-dimensional quantum-scale embedded nanostructures, such as quantum dots (QDs), toroids, and ellipsoids.

Laser-induced graphene (LIG) and laser-induced graphene scrolls (LIGS) materials and, more particularly to LIGS, methods of making LIGS (such as from polyimide (PI)), laser-induced removal of LIG and LIGS, and 3D printing of LIG and LIGS using a laminated object manufacturing (LOM) process.

A high-temperature silicon carbide device, along with an integrated circuit including the device and method of fabricating the device are described. For example, the method includes forming one of a source region and a drain region of a silicon carbide metal-oxide-semiconductor device. The method may include forming a gate structure adjacent to either one of the source region and the drain region. The gate structure may include an insulating layer. The method may further include forming the insulating layer with a first growth step performed in a pure oxygen environment and with a second growth step performed in a nitrous oxide environment.

Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate. Subsequent a first period of time, the methods may include providing a germanium-containing precursor to the processing region of the semiconductor processing chamber. The methods may include thermally reacting the silicon-containing precursor and the germanium-containing precursor at a temperature greater than or about 400° C. The methods may include forming a silicon-and-germanium-containing layer on the substrate.