Laser-induced graphene (LIG) and laser-induced graphene scrolls (LIGS) materials and, more particularly to LIGS, methods of making LIGS (such as from polyimide (PI)), laser-induced removal of LIG and LIGS, and 3D printing of LIG and LIGS using a laminated object manufacturing (LOM) process.

The present invention relates to methods for fabricating vertical homogenous and heterogeneous two-dimensional structures, the fabricated vertical two-dimensional structures, and methods of using the same. The methods demonstrated herein produce structures that are free standing and electrically isolated.

High quality Boron Nitride Nanotubes (BNNTs) may be synthesized by heating a boron melt target via one or more laser diodes, including laser diode stacks. The use of a diode stack and beam shaping optics to irradiate the boron melt eliminates the need for a conventional laser cavity as has been employed with previous embodiments. The diode arrangements facilitate managing power distribution on the born melt(s), nitrogen gas flows, and blackbody radiation that drive the BNNT self-assembly process. These parameters may be used for controlling the proportions and characteristics of boron species, a-BN particles, h-BN nanocages, and h-BN nano sheets in the as-synthesized BNNT material while enhancing the quality of the BNNTs.

An electronic device includes a spreading layer and a first contact layer formed over and contacting the spreading layer. The first contact layer is formed from a thermally conductive crystalline material having a thermal conductivity greater than or equal to that of an active layer material. An active layer includes one or more III-nitride layers. A second contact layer is formed over the active layer, wherein the active layer is disposed vertically between the first and second contact layers to form a vertical thin film stack.

A semiconductor layer of the present invention is a semiconductor layer including: a pn junction at which an n-type semiconductor (Al.sub.2O.sub.3 (n-type)) and a p-type semiconductor (Al.sub.2O.sub.3 (p-type)) are joined, the n-type semiconductor (Al.sub.2O.sub.3 (n-type)) having a donor level that is formed by causing an aluminum oxide film (Al.sub.2O.sub.3) to excessively contain aluminum (Al), the p-type semiconductor (Al.sub.2O.sub.3 (p-type)) having an acceptor level that is formed by causing an aluminum oxide film (Al.sub.2O.sub.3) to excessively contain oxygen (O).

Improved gate stack designs for Si and SiGe dual channel devices are provided. In one aspect, a method for forming a dual channel device includes: forming fins on a substrate, the fins including Si fins in combination with SiGe fins as dual channels of an analog device and a logic device, with the analog device and the logic device each having a Si fin and a SiGe fin; forming a silicon germanium oxide (SiGeOx) layer on the SiGe fins; annealing the SiGeOx layer to form a Si-rich layer on the SiGe fins via a reaction between SiGeOx and SiGe; and forming metal gates over the Si fins and over the Si-rich layer on the SiGe fins. A dual channel device is also provided.

The present disclosure relates to a wiring circuit, and a method for producing the wiring circuit, that includes graphite wiring having a specified thickness, a high electrical conductivity, and a high carrier mobility. The wiring circuit may include graphite wiring comprised of graphite where the graphite wiring has a thickness of 3 nm or more and less than 300 nm. The graphite may have an electrical conductivity along a graphite film plane direction of 18000 S/cm or more, and the graphite may have a carrier mobility along the graphite film plane direction of 9500 cm.sup.2/Vsec or more. The method for producing a wiring circuit may include steps of: (1) bonding a graphite film with a substrate; (2) plasma etching the graphite film to form a graphite thin film; and (3) etching the graphite thin film to form a wiring circuit.

A layered heterostructure, comprising alternating layers of different semiconductors, wherein one of the atom species of one of the semiconductors has a faster diffusion rate along an oxidizing interface than an atom species of the other semiconductor at an oxidizing temperature, can be used to fabricate embedded nanostructures with arbitrary shape. The result of the oxidation will be an embedded nanostructure comprising the semiconductor having slower diffusing atom species surrounded by the semiconductor having the higher diffusing atom species. The method enables the fabrication of low- and multi-dimensional quantum-scale embedded nanostructures, such as quantum dots (QDs), toroids, and ellipsoids.

Methods, systems, and apparatuses are described for integrated circuit-controlled ejection system (ICCES) for massively parallel integrated circuit assembly (MPICA). A unique Integrated Circuit (IC) die ejection head assembly system is described, which utilizes Three-Dimensional (3D) Printing/Etching to achieve very high-resolution manufacturing to meet the precision tolerances required for very small IC die sizes.

Embodiments of semiconductor structures for wafer flatness control and methods for using and forming the same are disclosed. In an example, a model indicative of a flatness difference of a wafer between a first direction and a second direction is obtained. The flatness difference is associated with one of a plurality of fabrication stages of a plurality of semiconductor devices on a front side of the wafer. A compensation pattern is determined for reducing the flatness difference based on the model. At the one of the plurality of the fabrication stages, a compensation structure is formed on a backside opposite to the front side of the wafer based on the compensation pattern to reduce the flatness difference.