A microelectronic device includes a gated graphene component. The gated graphene component has a graphitic layer containing one or more layers of graphene. The graphitic layer has a channel region, a first contact region adjacent to the channel region and a second contact region adjacent to the channel region. A patterned hexagonal boron nitride (hBN) layer is disposed on the graphitic layer above the channel region. A gate is located over the patterned hBN layer above the channel region. A first connection is disposed on the graphitic layer in the first contact region, and a second connection is disposed on the graphitic layer in the second contact region. The patterned hBN layer does not extend completely under the first connection or under the second connection. A method of forming the gated graphene component in the microelectronic device is disclosed.

A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.

Improved gate stack designs for Si and SiGe dual channel devices are provided. In one aspect, a method for forming a dual channel device includes: forming fins on a substrate, the fins including Si fins in combination with SiGe fins as dual channels of an analog device and a logic device, with the analog device and the logic device each having a Si fin and a SiGe fin; forming a silicon germanium oxide (SiGeOx) layer on the SiGe fins; annealing the SiGeOx layer to form a Si-rich layer on the SiGe fins via a reaction between SiGeOx and SiGe; and forming metal gates over the Si fins and over the Si-rich layer on the SiGe fins. A dual channel device is also provided.

Methods, systems, and apparatuses are described for integrated circuit-controlled ejection system (ICCES) for massively parallel integrated circuit assembly (MPICA). A unique Integrated Circuit (IC) die ejection head assembly system is described, which utilizes Three-Dimensional (3D) Printing/Etching to achieve very high-resolution manufacturing to meet the precision tolerances required for very small IC die sizes.

A microelectronic device includes a gated graphene component. The gated graphene component has a graphitic layer containing one or more layers of graphene. The graphitic layer has a channel region, a first contact region adjacent to the channel region and a second contact region adjacent to the channel region. A patterned hexagonal boron nitride (hBN) layer is disposed on the graphitic layer above the channel region. A gate is located over the patterned hBN layer above the channel region. A first connection is disposed on the graphitic layer in the first contact region, and a second connection is disposed on the graphitic layer in the second contact region. The patterned hBN layer does not extend completely under the first connection or under the second connection. A method of forming the gated graphene component in the microelectronic device is disclosed.

A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.

A method for manufacturing a semiconductor device includes: providing a carrier wafer and a silicon carbide wafer; forming a first graphene material on a first side of the silicon carbide wafer; bonding the first side of the silicon carbide wafer with the first graphene material to the carrier wafer; and splitting the silicon carbide wafer bonded to the carrier wafer into a silicon carbide layer thinner than the silicon carbide wafer and a residual silicon carbide wafer, the silicon carbide layer remaining bonded to the carrier wafer during the splitting.

Provided is a method of manufacturing a semiconductor device according to an embodiment, including implanting carbon ions into a predetermined region of a silicon substrate; forming a silicon carbide layer on the silicon substrate by performing heat treatment on the silicon substrate implanted with the carbon ions; and removing at least a portion of the silicon substrate to expose the silicon carbide layer.

A FinFET device includes a fin formed in a semiconductor substrate, a gate structure positioned above a portion of the fin, and source and drain regions positioned on opposite sides of the gate structure, wherein the semiconductor substrate includes a first semiconductor material. A silicon-carbide (SiC) semiconductor material is positioned above the fin in the source region and the drain region, wherein the silicon-carbide (SiC) semiconductor material is different from the first semiconductor material. A graphene contact is positioned on and in direct physical contact with the silicon-carbide (SiC) semiconductor material in each of the source region and the drain region, and first and second contact structures are conductively coupled to the graphene contacts in the source region and the drain region, respectively.

An object of the present invention is to provide a SiC semiconductor substrate capable of reducing a density of basal plane dislocations (BPD) in a growth layer, a manufacturing method thereof, and a manufacturing device thereof. The method includes: a strained layer removal process S10 that removes a strained layer introduced on a surface of a SiC substrate; and an epitaxial growth process S20 that conducts growth under a condition that a terrace width W of the SiC substrate is increased. When a SiC semiconductor substrate is manufactured in such processes, the basal plane dislocations BPD in the growth layer can be reduced, and a yield of a SiC semiconductor device can be improved.