A method of making a transistor for an integrated circuit includes providing a substrate and forming a dummy gate for the transistor within a gate trench on the substrate. The gate trench includes sidewalls, a trench bottom, and a trench centerline extending normally from a center portion of the trench bottom. The dummy gate is removed from the gate trench. A gate dielectric layer is disposed within the gate trench. A gate work-function metal layer is disposed over the gate dielectric layer, the work-function metal layer including a pair of corner regions proximate the trench bottom. An angled implantation process is utilized to implant a work-function tuning species into the corner regions at a tilt angle relative to the trench centerline, the tilt angle being greater than zero.

A method of manufacturing an integrated circuit device and an integrated circuit device prepared according to the method, the method including forming a silicon oxycarbonitride (SiOCN) material layer on an active region of a substrate, the forming the SiOCN material layer including using a precursor that has a bond between a silicon (Si) atom and a carbon (C) atom; etching a portion of the active region to form a recess in the active region; baking a surface of the recess at about 700 C. to about 800 C. under a hydrogen (H.sub.2) atmosphere, and exposing the SiOCN material layer to the atmosphere of the baking while performing the baking; and growing a semiconductor layer from the surface of the recess baked under the hydrogen atmosphere.

The present disclosure provides an apparatus for generating a processing gas by bubbling a raw material liquid with a carrier gas. The processing gas generated by the bubbling is taken out from a vapor-phase portion above a liquid-phase portion of the raw material liquid through a taking-out unit. A first temperature adjusting unit performs a temperature adjustment of the liquid-phase portion and a second temperature adjusting unit performs a temperature adjustment of the vapor-phase portion such that the temperature of the vapor-phase portion is higher than the temperature of the liquid-phase portion.

The disclosed method is suitable for producing a SiGe-on-insulator structure. According to some embodiments of the method, a layer comprising SiGe is deposited on silicon-on-insulator substrate comprising an ultra-thin silicon top layer. In some embodiments, the layer comprising SiGe is deposited by epitaxial deposition. In some embodiments, the SiGe epitaxial layer is high quality since it is produced by engineering the strain relaxation at the Si/buried oxide interface. In some embodiments, the method accomplishes elastic strain relaxation of SiGe grown on a few monolayer thick Si layer that is weakly bonded to the underline oxide.

Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500 C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500 C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.

A method of manufacturing an integrated circuit device and an integrated circuit device prepared according to the method, the method including forming a silicon oxycarbonitride (SiOCN) material layer on an active region of a substrate, the forming the SiOCN material layer including using a precursor that has a bond between a silicon (Si) atom and a carbon (C) atom; etching a portion of the active region to form a recess in the active region; baking a surface of the recess at about 700 C. to about 800 C. under a hydrogen (H.sub.2) atmosphere, and exposing the SiOCN material layer to the atmosphere of the baking while performing the baking; and growing a semiconductor layer from the surface of the recess baked under the hydrogen atmosphere.

Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500 C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500 C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.

A method of preparing a diamond crystal substrate for epitaxial deposition thereupon of a delta doping layer includes preparing an atomically smooth, undamaged diamond crystal substrate surface, which can be in the (100) plane, by polishing the surface and then etching the surface to remove subsurface damage caused by the polishing. The polishing can include a rough polish, for example in the (010) direction, followed by a fine polish, for example in the (011) direction, that removes the polishing tracks from the rough polishing. After etching the polished face can have a roughness Sa of less than 0.3 nm. An inductively coupled reactive ion etcher can apply the etching at a homogeneous etch rate using an appropriate gas mixture such as using argon and chlorine to remove between 0.1 and 10 microns of material from the polished surface.

Implementations described herein generally relate to methods and systems for depositing layer on substrates, and more specifically, to methods for forming boron or gallium-doped germanium on silicon-containing surfaces. In one implementation, a method of processing a substrate is provided. The method comprises exposing a substrate having an exposed silicon-germanium surface and an exposed dielectric surface to a pre-treatment process, selectively depositing a boron-doped or a gallium-doped layer on the exposed silicon-germanium surface and exposing the substrate to a post-treatment process.

Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500 C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500 C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.