An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.

This disclosure describes a method of making a tunnel barrier-based electronic device, in which the tunnel barrier and transport channel are made of the same materialgraphene. A homoepitaxial tunnel barrier/transport device is created using a monolayer chemically modified graphene sheet as a tunnel barrier on another monolayer graphene sheet. This device displays enhanced spintronic properties over heteroepitaxial devices and is the first to use graphene as both the tunnel barrier and channel.

In an aspect of the present invention, a graphene field-effect transistor (GFET) structure is formed. The GFET structure comprises a wider portion and a narrow extension portion extending from the wider portion that includes one or more graphene layers edge contacted to source and drain contacts, wherein the source and drain contacts are self-aligned to the one or more graphene layers.

Techniques for forming nanoribbon or bulk graphene-based SPR sensors are provided. In one aspect, a method of forming a graphene-based SPR sensor is provided which includes the steps of: depositing graphene onto a substrate, wherein the substrate comprises a dielectric layer on a conductive layer, and wherein the graphene is deposited onto the dielectric layer; and patterning the graphene into multiple, evenly spaced graphene strips, wherein each of the graphene strips has a width of from about 50 nanometers to about 5 micrometers, and ranges therebetween, and wherein the graphene strips are separated from one another by a distance of from about 5 nanometers to about 50 micrometers, and ranges therebetween. Alternatively, bulk graphene may be employed and the dielectric layer is used to form periodic regions of differing permittivity. A testing apparatus and method of analyzing a sample using the present SPR sensors are also provided.

An optical device includes a gallium and nitrogen containing substrate comprising a surface region configured in a (20-2-1) orientation, a (30-3-1) orientation, or a (30-31) orientation, within +/10 degrees toward c-plane and/or a-plane from the orientation. Optical devices having quantum well regions overly the surface region are also disclosed.

The semiconductor device includes a substrate, an epitaxial layer and a transistor structure. The substrate is a hexagonal crystal structure and has a top surface perpendicular to a c-axis. The top surface of the substrate includes a lattice plane that is parallel to the c-axis, in which the lattice plane is etched by using a developed photoresist, and an included angle between the top surface of the developed photoresist and the substrate is in a range from 30 degree to 60 degree. The epitaxial axis is located on the lattice plane. The transistor structure is located in the epitaxial layer, on the epitaxial layer and on a surface facing away from the epitaxial layer.

A graphene electronic device includes a gate insulating layer on a conductive substrate, a channel layer on the gate insulating layer, and a source electrode on one end of the channel layer and a drain electrode on another end of the channel layer. The channel layer includes a semiconductor layer and a graphene layer in direct contact with the semiconductor layer, and the graphene layer includes a plurality of graphene islands spaced apart from each other.

Methods of forming a graphene nanopattern, graphene-containing devices, and methods of manufacturing the graphene-containing devices are provided. A method of forming the graphene nanopattern may include forming a graphene layer on a substrate, forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer, forming a mask pattern from the block copolymer layer by removing one of a plurality of first region and a plurality of second regions of the block copolymer, and patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask. The block copolymer layer may be formed to directly contact the graphene layer. The block copolymer layer may be formed to directly contact a region of the substrate structure that is exposed on at least one side of the graphene layer.

There is provided a graphene sensor, preferably a graphene biosensor, comprising: a graphene layer structure provided on a non-metallic surface of a substrate, the graphene layer structure having an exposed, functionalised sample surface for receiving a sample for testing; first and second electrical contacts provided in contact with the graphene layer structure, and arranged on opposite sides of the functionalised sample surface; wherein each electrical contact is separated from the functionalised sample surface by an adjacent metal oxide layer, and wherein each electrical contact and adjacent metal oxide layer are capped with a passivating layer, whereby a sample for testing applied to the sample surface cannot contact the electrical contacts; and wherein the functionalised sample surface is devoid of photoresist.