Provided is a three-dimensional memory device including a substrate, first and second stacked structures and an etching stop layer. The substrate has a cell region and a periphery region. The first stacked structure is disposed on the cell region and the periphery region, and has a first vertical channel pillar on the cell region that penetrates through the first stacked structure. The second stacked structure is located on the first stacked structure, is disposed on the cell region and the periphery region, and has a second vertical channel pillar on the cell region that penetrates through the second stacked structure. The second vertical channel pillar is electrically connected to the first vertical channel pillar. The etching stop layer is located between the first and second stacked structures, is disposed on the cell region and extends onto the periphery region, and surrounds the lower portion of the second vertical channel pillar.

A single crystal CVD diamond component comprising: a surface, wherein at least a portion of said surface is formed of as-grown growth face single crystal CVD diamond material which has not been polished or etched and which has a surface roughness R.sub.a of no more than 100 nm; and a layer of NV.sup. defects, said layer of NV.sup. defects being disposed within 1 m of the surface, said layer of NV.sup. defects having a thickness of no more than 500 nm, and said layer of NV.sup. defects having a concentration of NV.sup. defects of at least 10.sup.5 NV.sup./cm.sup.2.

An optical device includes a gallium and nitrogen containing substrate comprising a surface region configured in a (20-2-1) orientation, a (30-3-1) orientation, or a (30-31) orientation, within +/10 degrees toward c-plane and/or a-plane from the orientation. Optical devices having quantum well regions overly the surface region are also disclosed.

A substrate processing apparatus includes a processing container configured to accommodate a plurality of substrates therein, a gas supply configured to supply a first raw material gas of a compound containing Si or Ge and H and a second raw material gas of a compound containing Si or Ge and a halogen element into the processing container; and an exhauster configured to evacuate an inside of the processing container, wherein the gas supply has a dispersion nozzle provided with a plurality of gas holes for discharging the first raw material gas and the second raw material gas, and the substrate processing apparatus further comprises a heater configured to heat the first raw material gas and the second raw material gas in the dispersion nozzle.

A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area. A first dielectric layer and a second dielectric layer are sequentially formed to cover the material layer, wherein a top surface of the first dielectric layer in the high pattern density area is higher than a top surface of the first dielectric layer in the low pattern density area, thereby a thickness of the second dielectric layer in the low pattern density area being thicker than a thickness of the second dielectric layer in the high pattern density area. An etching back process is performed to remove the second dielectric layer and the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer.

A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area. A first dielectric layer and a second dielectric layer are sequentially formed to cover the material layer, wherein a top surface of the first dielectric layer in the high pattern density area is higher than a top surface of the first dielectric layer in the low pattern density area, thereby a thickness of the second dielectric layer in the low pattern density area being thicker than a thickness of the second dielectric layer in the high pattern density area. An etching back process is performed to remove the second dielectric layer and the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer.

An electrical isolation process, includes receiving a substrate including a layer of carbon-rich material on silicon, and selectively removing regions of the substrate to form mutually spaced islands of the carbon-rich material on the silicon. The layer of carbon-rich material on silicon includes the layer of carbon-rich material on an electrically conductive layer of silicon on an electrically insulating material. Selectively removing regions of the substrate includes removing the carbon-rich material and at least a portion of the electrically conductive layer of silicon from those regions to provide electrical isolation between the islands of carbon-rich material on silicon.

A method of catalyst-assisted chemical etching with a vapor-phase etchant has been developed. In one approach, a semiconductor substrate including a patterned titanium nitride layer thereon is heated, and an oxidant and an acid are evaporated to form a vapor-phase etchant comprising an oxidant vapor and an acid vapor. The semiconductor substrate and the patterned titanium nitride layer are exposed to the vapor-phase etchant during the heating of the semiconductor substrate. The vapor-phase etchant diffuses through the patterned titanium nitride layer, and titanium nitride-covered regions of the semiconductor substrate are etched. Thus, an etched semiconductor structure is formed.

A silicon layer etchant composition and associated methods, the composition including about 1 wt % to about 20 wt % of an alkylammonium hydroxide; about 1 wt % to about 30 wt % of an amine compound; about 0.01 wt % to about 0.2 wt % of a nonionic surfactant including both a hydrophobic group and a hydrophilic group; and water, all wt % being based on a total weight of the silicon layer etchant composition.

Methods for etching features into carbon material using a metal-doped carbon-containing hard mask to reduce and eliminate redeposition of silicon-containing residues are provided herein. Methods involve depositing a metal-doped carbon-containing hard mask over the carbon material prior to etching the carbon material, patterning the metal-doped carbon-containing hard mask, and using the patterned metal-doped carbon-containing hard mask to etch the carbon material such that the use of a silicon-containing mask during etch of the carbon material is eliminated.