A metal-insulator-metal (MIM) capacitor and a process of forming the same are disclosed. The process includes steps of: forming a lower electrode that provides a lower layer and an upper layer; forming an opening in the upper layer; forming a supplemental layer on the lower layer exposed in the opening; heat treating the lower electrode and the supplemental layer; covering at least the upper layer of the lower electrode with an insulating film; and forming an upper electrode in an area on the insulating film, where the area is not overlapped with the supplemental layer and within 100 m at most from the supplemental layer. A feature of the MIM capacitor is that the supplemental layer is made of a same metal as a metal contained in the lower layer of the lower electrode.

Some embodiments include methods of forming integrated assemblies. First conductive structures are formed within an insulative support material and are spaced along a first pitch. Upper regions of the first conductive structures are removed to form first openings extending through the insulative support material and over lower regions of the first conductive structures. Outer lateral peripheries of the first openings are lined with spacer material. The spacer material is configured as tubes having second openings extending therethrough to the lower regions of the first conductive structures. Conductive interconnects are formed within the tubes. Second conductive structures are formed over the spacer material and the conductive interconnects. The second conductive structures are spaced along a second pitch, with the second pitch being less than the first pitch. Some embodiments include integrated assemblies.

Amorphous tungsten nitride compounds, products, and methods of manufacture, as well as devices incorporating the same are disclosed herein. An example electro-mechanical device includes a first gate, a first drain, and a source having a completely amorphous metal tungsten nitride film cantilever. The cantilever extends from an anchor of the source transversely to the first gate and the first drain.

The disclosure provides a liquid crystal display panel, an array substrate and a manufacturing method thereof. In the method, controllable resistance spacer layers are formed on at least one of a source doped region and a drain doped region of a low temperature polysilicon active layer. When a turn-on signal is not applied to the gate layer, the controllable resistance spacer layers serve as a blocking action for a flowing current; and when the turn-on signal is applied to the gate layer, the controllable resistance spacer layers serve as a conducting action for the flowing current, such that contact regions formed of the controllable resistance spacer layers are respectively connected with the corresponding source layer and the corresponding drain through the controllable resistance spacer layers. Therefore, the disclosure is capable of effectively decreasing a leakage of a thin film transistor.

A method of manufacturing a semiconductor element includes forming a first silicon oxide film on a semiconductor wafer under a first film forming condition; forming a second silicon oxide film on the first silicon oxide film under a second film forming condition, a density of the second silicon oxide film being lower than a density of the first silicon oxide film; coating, with a photoresist, a region including the second silicon oxide film; exposing the photoresist using a photomask having an aperture and being disposed such that at least a portion of an edge of the aperture is disposed on the second silicon oxide film; removing a portion of the photoresist to form a photoresist pattern that has an overhang shape in a cross-section of the photoresist pattern; forming an electrode film on a region including the photoresist pattern; and performing lift-off by removing the photoresist pattern.

A metal-insulator-metal (MIM) capacitor and a process of forming the same are disclosed. The process includes steps of: forming a lower electrode that provides a lower layer and an upper layer; forming an opening in the upper layer; forming a supplemental layer on the lower layer exposed in the opening; heat treating the lower electrode and the supplemental layer; covering at least the upper layer of the lower electrode with an insulating film; and forming an upper electrode in an area on the insulating film, where the area is not overlapped with the supplemental layer and is within 100 m at most from the supplemental layer. A feature of the MIM capacitor is that the supplemental layer is made of a same metal as a metal contained in the lower layer of the lower electrode.

Some embodiments include methods of forming integrated assemblies. First conductive structures are formed within an insulative support material and are spaced along a first pitch. Upper regions of the first conductive structures are removed to form first openings extending through the insulative support material and over lower regions of the first conductive structures. Outer lateral peripheries of the first openings are lined with spacer material. The spacer material is configured as tubes having second openings extending therethrough to the lower regions of the first conductive structures. Conductive interconnects are formed within the tubes. Second conductive structures are formed over the spacer material and the conductive interconnects. The second conductive structures are spaced along a second pitch, with the second pitch being less than the first pitch. Some embodiments include integrated assemblies.

Disclosed are an adhesive transparent electrode and a method of fabricating the same. More particularly, an adhesive transparent electrode according to an embodiment of the present disclosure includes a substrate and an adhesive silicone-based polymer matrix, in which a metal nanowire network is embedded, deposited on the substrate, wherein the adhesive silicone-based polymer matrix includes a silicone-based polymer including a silicone-based polymer base and a silicone-based polymer crosslinker; and a non-ionic surfactant.

A manufacturing method of a touch panel includes the steps of providing a substrate, forming a first conductive film on the substrate, forming a first mask on the first conductive film, etching the first conductive film to form electrode portions and lower intersect portions of the touch panel, forming an insulating film made of a negative resist on the first conductive film, and forming a contact hole above the electrode portion by removing the insulating film. The steps further include forming a second conductive film on the insulating film, forming a second mask on the second conductive film, etching the second conductive film to form an upper intersect portion connected between two adjacent electrode portions via the contact hole and intersecting with the lower intersect portion, and forming protective film on the second conductive film.

Some embodiments include methods of forming integrated assemblies. First conductive structures are formed within an insulative support material and are spaced along a first pitch. Upper regions of the first conductive structures are removed to form first openings extending through the insulative support material and over lower regions of the first conductive structures. Outer lateral peripheries of the first openings are lined with spacer material. The spacer material is configured as tubes having second openings extending therethrough to the lower regions of the first conductive structures. Conductive interconnects are formed within the tubes. Second conductive structures are formed over the spacer material and the conductive interconnects. The second conductive structures are spaced along a second pitch, with the second pitch being less than the first pitch. Some embodiments include integrated assemblies.