A manufacturing method of a semiconductor device is provided by forming a trench in a surface of a SiC substrate, positioning a protective substrate to cover the trench, and annealing the SiC substrate and the protective substrate.

A semiconductor device according to the embodiments includes a SiC layer having a first plane, an insulating layer, and a region between the first plane and the insulating layer, the region including at least one element in the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium), a full width at half maximum of a concentration peak of the element being equal to or less than 1 nm, and when a first area density being an area density of Si (silicon) and C (carbon) including a bond which does not bond with any of Si and C in the SiC layer at the first plane and a second area density being an area density of the element, the second area density being equal to or less than of the first area density.

A trench has first to third side surfaces respectively constituted of first to third semiconductor layers. A first side wall portion included in a first insulating film has first to third regions respectively located on the first to third side surfaces. A second insulating film has a second side wall portion located on the first side wall portion. The second side wall portion has one end and the other end, the one end being connected to the second bottom portion of the second insulating film, the other end being located on one of the first and second regions, the other end being separated from the third region.

A semiconductor device having a voltage resistant structure in a first aspect of the present invention is provided, comprising a semiconductor substrate, a semiconductor layer on the semiconductor substrate, a front surface electrode above the semiconductor layer, a rear surface electrode below the semiconductor substrate, an extension section provided to a side surface of the semiconductor substrate, and a resistance section electrically connected to the front surface electrode and the rear surface electrode. The extension section may have a lower permittivity than the semiconductor substrate. The resistance section may be provided to at least one of the upper surface and the side surface of the extension section.

A passivation method for a silicon carbide (SiC) surface may include steps of providing a silicon carbide surface, depositing a thin metal layer on the silicon carbide surface, forming a first passivation layer on the metal layer at low temperature, and generating a dielectric layer by a reaction between a gas/liquid ambient and the thin metal layer. In one embodiment, the thin metal layer is deposited on the silicon carbide surface by sputtering, e-beam evaporation, electroplating, etc. In another embodiment, the metal may include, but not limited to, aluminum, magnesium, etc. In a further embodiment, the passivation layer can be a low temperature oxide and/or nitride layer. In still a further embodiment, the dielectric layer can be aluminum oxide, titanium di-oxide etc. The passivation method for a silicon carbide (SiC) may further include a step of forming a second passivation layer on the first passivation layer.

A method for manufacturing a SiC semiconductor device includes the steps of: forming an impurity region in a SiC layer; forming a first carbon layer on a surface of the SiC layer having the impurity region formed therein, by selectively removing silicon from the surface; forming a second carbon layer on the first carbon layer; and heating the SiC layer having the first carbon layer and the second carbon layer formed therein.

A method of manufacturing a silicon carbide semiconductor device includes a step of preparing a silicon carbide substrate having a first main surface and a second main surface located opposite to the first main surface, a step of forming a doped region in the silicon carbide substrate by doping the first main surface with an impurity, a step of forming a first protecting film on the doped region at the first main surface, and a step of activating the impurity included in the doped region by annealing with the first protecting film having been formed, the step of forming a first protecting film including a step of disposing a material which will form the first protecting film and in which the concentration of a metal element is less than or equal to 5 g/kg on the first main surface.

A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

A SIC transistor device includes a silicon-carbide semiconductor substrate having a plurality of first doped regions laterally spaced apart from one another and beneath a main surface of the substrate, a second doped region extending from the main surface to a third doped region that is above the first doped regions, and a plurality of fourth doped regions in the substrate extending from the main surface to the first doped regions. The second doped region has a first conductivity type. The first, third and fourth doped regions have a second conductivity type opposite the first conductivity type. A gate trench extends through the second and third doped regions. The gate trench has sidewalls, a bottom and rounded corners between the bottom and the sidewalls.

Methods, systems, and devices are disclosed for implementing high power circuits and semiconductor devices. In one aspect, a method for fabricating a silicon carbide semiconductor device includes forming a thin epitaxial layer of a nitrogen doped SiC material on a SiC epitaxial layer formed on a SiC substrate, and thermally growing an oxide layer to form an insulator material on the nitrogen doped SiC epitaxial layer, in which the thermally grown oxide layer results in at least partially consuming the nitrogen doped SiC epitaxial layer in the oxide layer to produce an interface including nitrogen between the SiC epitaxial layer and the oxide layer.