A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

A semiconductor structure is provided. The semiconductor structure includes an insulator layer, first and second field-effect transistor devices, an isolation field-effect transistor device, front-side gate and back-side gate contacts. Each of the first and second field-effect transistor devices and the isolation field-effect transistor device includes a fin structure and first and second epitaxial source/drain structures. The fin structure includes channel layers and a gate structure that is wrapped around the channel layers. The first and second epitaxial source/drain structures are connected to opposite sides of the channel layers. The isolation field-effect transistor device is kept in the off-state. The front-side gate contact is formed on the first field-effect transistor device and electrically connected to the gate structure of the first field-effect transistor device. The back-side gate contact is formed passing through the insulator layer and electrically connected to the gate structure of the isolation field-effect transistor device.

Herein, a method of forming a semiconductor device may comprise forming a semiconductor substrate comprising silicon carbide at a surface thereof, cleaning a surface area of the semiconductor substrate by removing oxide species, carbon clusters, or other contaminants, and forming a dielectric layer above the cleaned surface of the semiconductor substrate. The method further provides a surface passivation at the interface of the cleaned surface of the semiconductor substrate and the dielectric layer.

The disclosure relates to a semiconductor die, comprising a silicon carbide (SiC) semiconductor body; a passivation system on a first side of the SiC semiconductor body; the passivation system comprising an inorganic passivation layer system and an organic layer on the inorganic passivation layer system, a lateral edge of the inorganic passivation layer system arranged on the SiC semiconductor body, wherein the inorganic passivation layer system is laterally set back under the organic layer, the lateral edge of the inorganic passivation layer system being covered by the organic layer.