A passivation method for a silicon carbide (SiC) surface may include steps of providing a silicon carbide surface, depositing a thin metal layer on the silicon carbide surface, forming a first passivation layer on the metal layer at low temperature, and generating a dielectric layer by a reaction between a gas/liquid ambient and the thin metal layer. In one embodiment, the thin metal layer is deposited on the silicon carbide surface by sputtering, e-beam evaporation, electroplating, etc. In another embodiment, the metal may include, but not limited to, aluminum, magnesium, etc. In a further embodiment, the passivation layer can be a low temperature oxide and/or nitride layer. In still a further embodiment, the dielectric layer can be aluminum oxide, titanium di-oxide etc. The passivation method for a silicon carbide (SiC) may further include a step of forming a second passivation layer on the first passivation layer.

According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.

A method for reducing defects of an electronic component using a supercritical fluid includes recrystallizing and rearranging grains in the electronic component by introducing the supercritical fluid doped with H.sub.2S together with an electromagnetic wave into a cavity. The cavity has a temperature above a critical temperature of the supercritical fluid and a pressure above a critical pressure of the supercritical fluid.

A semiconductor device includes: a first conductivity type semiconductor substrate made of silicon carbide; a second conductivity type body region in a device region of the semiconductor substrate; a first conductivity type source region formed in the body region; and a gate electrode formed on the body region through gate insulating films. The semiconductor device further includes, in a termination region of the semiconductor substrate, second conductivity type RESURF layers, and an edge termination region formed in the RESURF layers. Then, the RESURF layers and a front surface of the semiconductor substrate adjacent to the RESURF layers are covered by an oxidation-resistant insulating film.

A resist protective film protects front surfaces of a front electrode and a polyimide protective film. With a BG tape affixed to the resist protective film, a semiconductor substrate is ground from a rear surface to a predetermined product thickness. After the BG tape is removed, a predetermined diffusion region is formed in a surface layer at the ground rear surface of the semiconductor substrate. The resist protective film is heated to and maintained at a temperature of at least 100 degrees C., for evaporating water in the resist protective film. Laser is irradiated from the rear surface of the semiconductor substrate, activating an impurity of the diffusion region. The resist protective film is removed. Thus, during heat treatment for impurity activation at one main surface of the semiconductor wafer, deterioration, peeling, and deformation of the resist protective film protecting the other main surface of the semiconductor wafer may be suppressed.

A method of forming a semiconductor device includes etching a semiconductor layer to form a plurality of mesa stripes in the semiconductor layer. The plurality of mesa stripes extend in a first direction and include mesa sidewalls that extend in the first direction and mesa surfaces at opposite ends of the mesa stripes. An additional mesa region is formed at an end of at least one of the mesa stripes. The additional mesa region is electrically insulated from the at least one of the mesa stripes. A semiconductor device structure includes a plurality of mesa stripes that extend in a first direction and include mesa sidewalls that extend in the first direction and mesa end surfaces at opposite ends of the mesa stripes. An additional mesa region that is electrically insulated from the at least one of the mesa stripes is at an end of at least one of the mesa stripes.

The present disclosure provides a silicon carbide (SiC) opto-thyristor and a method for manufacturing the same. The SiC opto-thyristor includes a SiC substrate, a SiC light emitter and a SiC light-sensitive thyristor. In the method, a SiC epitaxy is mainly formed on the SiC substrate with the doped P-type and N-type semiconductor materials to define the regions for forming the SiC light emitter and the basic structures of the SiC light-sensitive thyristor. A passivation layer is deposited. Conducting channels for the SiC light emitter and the SiC light-sensitive thyristor are formed by an etching process. After patterning a metal conductor layer, a structure of electrical contacts of the SiC light emitter and the SiC light-sensitive thyristor is formed. Then, terminals of an input voltage and an output voltage of the silicon carbide opto-thyristor are formed after a wire bonding process upon the electrical contacts. Finally, a packaging process is performed.

An electronic device is provided. The electronic device includes a first substrate, an insulating layer, a first conductive layer and a second conductive layer. The insulating layer is overlapped with the first substrate. The second conductive layer contacts with the first conductive layer. The first conductive layer and the second conductive layer are disposed between the first substrate and the insulating layer. The second conductive layer is disposed between the first conductive layer and the insulating layer. Moreover, a thermal expansion coefficient of the second conductive layer is between a thermal expansion coefficient of the first conductive layer and a thermal expansion coefficient of the insulating layer.

A semiconductor device of an embodiment includes a silicon carbide layer having a first plane and a second plane; a trench having a first side face, a second side face, and a bottom face; a first silicon carbide region of a first conductivity type; a second silicon carbide region and a third silicon carbide region of a second conductivity type, the third silicon carbide region and the second silicon carbide region sandwiching the trench; a sixth silicon carbide region of a second conductivity type in contact with the second side face and the bottom face; and a gate electrode in the trench. The first side face has a first region having a first inclination angle. The off angle of the first region with respect to a {0-33-8} face is no more than 2 degrees. A second inclination angle of the second side face is larger the first inclination angle.

A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.