Patent classifications
H01L21/0455
SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SILICON CARBIDE SEMICONDUCTOR DEVICE
In a silicon carbide semiconductor device, a trench penetrates a source region and a first gate region and reaches a drift layer. On an inner wall of the trench, a channel layer of a first conductivity-type is formed by epitaxial growth. On the channel layer, a second gate region of a second conductivity-type is formed. A first depressed portion is formed at an end portion of the trench to a position deeper than a thickness of the source region so as to remove the source region at the end portion of the trench. A corner portion of the first depressed portion is covered by a second conductivity-type layer.
Semiconductor device
The present invention provides a semiconductor device that prevents destruction due to an avalanche breakdown and that has a high tolerance against breakdown by configuring the device so as to have a punch-through breakdown function therein and such that the breakdown voltage of a punch-through breakdown is lower than an avalanche breakdown voltage so that an avalanche breakdown does not occur.
METHODS FOR PREPARING LAYERED SEMICONDUCTOR STRUCTURES
Methods for preparing layered semiconductor structures are disclosed. The methods may involve pretreating an ion-implanted donor wafer by annealing the ion-implanted donor wafer to cause a portion of the ions to out-diffuse prior to wafer bonding. The donor structure may be bonded to a handle structure and cleaved without re-implanting ions into the donor structure.
SILICON-CARBIDE TRENCH GATE MOSFETS
In a general aspect, an apparatus can include a silicon carbide (SiC) trench gate MOSFET with improved operation due, at least in part, to a reduced gate capacitance. In the SiC trench gate MOSFET, a thick gate oxide can be formed on a bottom surface of the gate trench and a built-in channel, having a vertical portion and a lateral portion, can be formed to electrically connect a vertical inversion-layer channel, such as in a channel stopper layer, to a vertical JFET channel region and a drift region.
Flexible monolithic all polycrystalline silicon carbide neural interface device and method of manufacture
An implantable, conformal, neural interface device fabricated completely from neuro-compatible SiC and method of manufacture thereof, includes at least one elongated probe to be placed in a brain of a subject of interest, the at least one elongated probe comprising a plurality of electrodes positioned on a surface of the elongated probe, each of the plurality of electrodes comprising a conductive mesa consisting of polycrystalline silicon carbide (SiC), an insulative layer consisting of amorphous SiC, the insulative layer positioned to surround the conductive mesa absent a window through the amorphous SiC exposing a surface of the conductive mesa. The elongated probe is integral with, the probe base comprising a plurality of contact pads, each of the plurality of contact pads in electrical communication with one of the plurality of electrodes.