Patent classifications
H01L21/0455
Vertical insulated gate turn-off thyristor with intermediate p+ layer in p-base formed using epitaxial layer
An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an n layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. After forming the p-well, boron ions are implanted into the exposed surface of the p-well to form a p+ region. The n-epi layer is then grown over the p-well and the p+ region, and the boron in the p+ region is diffused upward into the n-epi layer and downward to form an intermediate p+ region. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter) and the overall dopant concentration and thickness of the p-type base to optimize the thyristor's performance.
LASER IRRADIATION METHOD AND LASER IRRADIATION SYSTEM
A laser irradiation method of irradiating, with a pulse laser beam, an irradiation object in which an impurity source film is formed on a semiconductor substrate includes: reading fluence per pulse of the pulse laser beam with which a rectangular irradiation region set on the irradiation object is irradiated and the number of irradiation pulses the irradiation region is irradiated, the fluence being equal to or larger than a threshold at or beyond which ablation potentially occurs to the impurity source film when the irradiation object is irradiated with pulses of the pulse laser beam in the irradiation pulse number and smaller than a threshold at or beyond which damage potentially occurs to the surface of the semiconductor substrate; calculating a scanning speed Vdx; and moving the irradiation object at the scanning speed Vdx relative to the irradiation region while irradiating the irradiation region with the pulse laser beam at the repetition frequency f.
LASER RADIATION SYSTEM
A laser radiation optical system for laser doping and post-annealing, the laser radiation system including A. a laser apparatus configured to generate pulsed laser light that belongs to an ultraviolet region, B. a stage configured to move a radiation receiving object in an at least one scan direction, the radiation receiving object being an impurity source film containing at least an impurity element as a dopant and formed on a semiconductor substrate, and C. an optical system including a beam homogenizer configured to shape the beam shape of the pulsed laser light into a rectangular shape and generate a beam for laser doping and a beam for post-annealing that differ from each other in terms of a first beam width in the scan direction but have the same second beam width perpendicular to the scan direction.
Doping system, doping method and method for manufacturing silicon carbide semiconductor device
A doping system includes a light source to emit an optical pulse; a light source controller connected to the light source, to control an energy density of the optical pulse; and a beam adjusting unit to irradiate the optical pulse to a surface of a doping-object made of silicon carbide on which an impurity-containing source-film containing impurity atoms is deposited. The light source controller irradiates a first optical pulse to the impurity-containing source-film so as to form a reaction-product layer in the doping-object, and irradiates a second optical pulse having an energy density higher than an energy density of the first optical pulse, so as to introduce the impurity atoms into the target through the reaction-product layer.
SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SILICON CARBIDE SEMICONDUCTOR DEVICE
A p-type base region is configured by a p.sup.-type channel region and a p-type high-impurity-concentration region adjacent to the channel region in a horizontal direction. A point having a highest impurity concentration in the high-concentration region is located at a position separated from a lower surface of an n.sup.++-type source region. The impurity concentration in the high-impurity-concentration region decreases toward the front surface of the semiconductor substrate and the rear surface of the semiconductor substrate in the depth direction. The impurity concentration in the high-impurity-concentration region decreases toward the low-impurity-concentration region in a direction parallel to the front surface of the semiconductor substrate.
SEMICONDUCTOR DEVICE INCLUDING SILICON CARBIDE BODY AND METHOD OF MANUFACTURING
A semiconductor device includes a silicon carbide body that includes a first section and a second section. The first section is adjacent to the second section. A drift region is formed in the first section and the second section. A lattice defect region is in a portion of the drift region in the second section. A first density of lattice defects, which include interstitials and vacancies in the lattice defect region, is at least double a second density of lattice defects, which include interstitials and vacancies in a portion of the drift region outside the lattice defect region.
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
A semiconductor device and its manufacturing method, relating to semiconductor techniques. The semiconductor device manufacturing method comprises: forming a patterned first hard mask layer on a substrate to define a position for buried layers; conducting a first ion implantation using the first hard mask layer as a mask to form a first buried layer and a second buried layer both having a first conductive type and separated from each other at two sides of the first hard mask layer in the substrate; conducting a second ion implantation to form a separation region with a second conductive type opposite to the first conductive type in the substrate between the first and the second buried layers; removing the first hard mask layer; and forming a semiconductor layer on the substrate. This inventive concept reduces an area budget of a substrate and simplifies the manufacturing process.
Impurity adding apparatus, impurity adding method, and semiconductor element manufacturing method
An impurity-doping apparatus is provided with: a supporting plate which supports a semiconductor substrate; a wall-like block disposed above the supporting plate floating away from the semiconductor substrate, the wall-like block implements a recess inside so as to establish a space for a solution region containing impurity elements, the solution region is localized on an upper surface of the semiconductor substrate, the upper surface being opposite to an bottom surface facing to the supporting plate; and a laser optical system, configured to irradiate a laser beam onto the upper surface of the semiconductor substrate, through the solution region surrounded by the wall-like block, wherein the impurity elements are doped into a part of the semiconductor substrate by irradiation of the laser beam.
Laser doping apparatus and laser doping method
The laser doping apparatus may irradiate a predetermined region of a semiconductor material with a pulse laser beam to perform doping. The laser doping apparatus may include: a solution supplying system configured to supply dopant-containing solution to the predetermined region, and a laser system including at least one laser device configured to output the pulse laser beam to be transmitted by the dopant-containing solution, and a time-domain pulse waveform changing apparatus configured to control a time-domain pulse waveform of the pulse laser beam.
Semiconductor Device and Method
Methods are disclosed for forming a multi-layer structure including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. According to embodiments, during a deposition of semiconductor layers, the process is controlled to remain at low temperatures such that an inter-diffusion rate between the materials of the deposited layers is managed to provide diffusion interfaces with abrupt Si/SiGe interfaces. The highly controlled interfaces and first and second layers provide a multi-layer structure with improved etching selectivity. In an embodiment, a gate all-around (GAA) transistor is formed with horizontal nanowires (NWs) from the multi-layer structure with improved etching selectivity. In embodiments, horizontal NWs of a GAA transistor may be formed with substantially the same size diameters and silicon germanium (SiGe) NWs may be formed with all-in-one silicon (Si) caps.