Implementations of a method of forming a plurality of semiconductor devices on a semiconductor substrate may include: providing a semiconductor substrate having a first surface, a second surface, a size, and a thickness where the second surface opposes the first surface and the thickness is between the first surface and the second surface. The method may include processing the semiconductor substrate through a plurality of semiconductor device fabrication processes to form a plurality of semiconductor devices on the first surface. The thickness may be between 100 microns and 575 microns and the size may be 150 mm. The semiconductor substrate may not be coupled with a carrier or support.

Silicon carbide (SiC) wafers and related methods are disclosed that include large diameter SiC wafers with wafer shape characteristics suitable for semiconductor manufacturing. Large diameter SiC wafers are disclosed that have reduced deformation related to stress and strain effects associated with forming such SiC wafers. As described herein, wafer shape and flatness characteristics may be improved by reducing crystallographic stress profiles during growth of SiC crystal boules or ingots. Wafer shape and flatness characteristics may also be improved after individual SiC wafers have been separated from corresponding SiC crystal boules. In this regard, SiC wafers and related methods are disclosed that include large diameter SiC wafers with suitable crystal quality and wafer shape characteristics including low values for wafer bow, warp, and thickness variation.

There is provided a reverse-blocking semiconductor device that has a simple configuration, that is capable of improving a yield in a manufacturing process, and that secures a reverse withstand voltage by using a Schottky junction, and there is provided a method for manufacturing the reverse-blocking semiconductor device. A semiconductor device is provided that includes a first conductivity type semiconductor layer that has a front surface, a rear surface on an opposite side of the front surface, and an end surface, a MIS transistor structure formed at a front-surface portion of the semiconductor layer, a first electrode that forms a Schottky junction with a part of the semiconductor layer in the rear surface of the semiconductor layer, and an electric-field relaxation region that is formed to reach the rear surface from the front surface of the semiconductor layer in a peripheral region surrounding an active region in which the MIS transistor structure is formed and that is either a high-resistance region having higher resistance than the semiconductor layer or a second conductivity type impurity region.

A semiconductor device includes a trench structure extending from a first surface into a semiconductor body composed of silicon carbide. The trench structure includes an electrode and between the electrode and the first surface a gate electrode. A shielding region adjoining the electrode forms a first pn junction with a drift structure formed in the semiconductor body. A Schottky contact is formed between the drift structure and a first contact structure.

A method of manufacturing a silicon carbide substrate having a parallel pn layer. The method includes preparing a starting substrate containing silicon carbide, forming a first partial parallel pn layer on the starting substrate by a trench embedding epitaxial process, stacking a second partial parallel pn layer by a multi-stage epitaxial process on the first partial parallel pn layer, and stacking a third partial parallel pn layer on the second partial parallel pn layer by another trench embedding epitaxial process. Each of the first, second and third partial parallel pn layers is formed to include a plurality of first-conductivity-type regions and a plurality of second-conductivity-type regions alternately disposed in parallel to a main surface of the silicon carbide substrate. The first-conductivity-type regions of the first and third partial parallel pn layers face each other in a depth direction of the silicon carbide substrate, and the second-conductivity-type regions partial parallel pn layers face each other in the depth direction.

A method includes providing a first layer of epitaxial silicon carbide supported by a silicon carbide substrate, providing a second layer of epitaxial silicon carbide on the first layer, forming a plurality of semiconductor devices in the second layer, and separating the substrate from the second layer at the first layer. The first layer includes a plurality of voids.

A power semiconductor device includes a silicon carbide substrate and has at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The power semiconductor device further includes an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts. Each pit of the pattern of pits has a depth that extends short of the first layer.

A system and method for fabricating an orifice in a multi-layered semiconductor substrate and singulation of the semiconductor substrate includes adding a sacrificial layer of material to a first surface of a semiconductor substrate; subsequently, removing a first radius of a first depth of material from the semiconductor substrate along a direction normal to the first surface, the removal of the first depth of material uses a first removal technique that removes the first depth of material; and removing a second radius of a second depth of material from the semiconductor substrate along the direction normal to the first surface based on the removal of the first depth of material, the removal of the second depth of material uses a second removal technique.

According to one embodiment, a method for manufacturing a substrate is disclosed. The method can include preparing a structure body. The structure body includes a first semiconductor member and a second semiconductor member. The first semiconductor member includes silicon carbide including a first element. The second semiconductor member includes silicon carbide including a second element. The first element includes at least one selected from a first group consisting of N, P, and As. The second element includes at least one selected from a second group consisting of B, Al, and Ga. The method can include forming a hole that extends through the second semiconductor member and reaches the first semiconductor member. In addition, the method can include forming a third semiconductor member in the hole. The third semiconductor member includes silicon carbide including a third element. The third element includes at least one selected from the first group.

A method for fabricating an orifice in a semiconductor which can include: removing a first depth of the semiconductor using a first material removal technique and removing a second depth of the semiconductor using a second material removal technique. The method can optionally include: adding a sacrificial layer of material and reducing a depth of the semiconductor by a friction-based material removal technique. In examples, the method fabricates a wafer-scale processor with a set of fastening features.