A power semiconductor device includes a silicon carbide substrate and at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The device includes a stop layer that is disposed at least in part laterally between the pits. The device further comprising an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts, wherein the ohmic metal contacts at least parts of the stop layer.

A method for forming a polycrystalline semiconductor layer includes forming a plurality of spacers over a dielectric layer, etching the dielectric layer using the plurality of spacers as an etch mask to form a recess in the dielectric layer, depositing an amorphous semiconductor layer over the plurality of spacers and the dielectric layer to fill the recess, and recrystallizing the amorphous semiconductor layer to form a polycrystalline semiconductor layer.

The present disclosure provides a method for forming a thermoelectric device, comprising providing a semiconductor substrate and providing a first layer of an etching material adjacent to the semiconductor substrate. The etching material facilitates the etching of the semiconductor substrate upon exposure to an oxidizing agent and a chemical etchant. Next, a second layer of a semiconductor oxide is provided adjacent to the first layer, and the second layer is patterned to form a pattern of holes or wires. The second layer and first layer are then sequentially etched to expose portions of the semiconductor substrate. Exposed portions of the semiconductor substrate are then contacted with an oxidizing agent and a chemical etchant to transfer the pattern to the semiconductor substrate.

An embodiment relates to a method comprising obtaining a SiC substrate comprising a N+ substrate and a N drift layer; depositing a first hard mask layer on the SiC substrate and patterning the first hard mask layer; performing a p-type implant to form a p-well region; depositing a second hard mask layer on top of the first hard mask layer; performing an etch back of at least the second hard mask layer to form a sidewall spacer; implanting N type ions to form a N+ source region that is self-aligned; and forming a MOSFET.

A method for manufacturing a SiC epitaxial wafer is provided. The method includes an observation step of observing a principal surface of a SiC substrate and identifying the presence or absence of a scratch having a depth of a predetermined value or more, a protrusion having a height of a predetermined value or more, or a foreign object having a height of a predetermined value or more, a polishing step of polishing the principal surface of the SiC substrate when it is identified that there is a scratch, the protrusion, or a foreign object and a layer forming step of forming a SiC epitaxial layer on the principal surface of the SiC substrate.

The semiconductor device includes: a substrate, an n-type drift region formed on a main surface of the substrate; a p-type well region, an n-type drain region and an n-type source region each formed in the drift region to extend from a second main surface of the drift region opposite to the first main surface of the drift region in contact with the substrate in a direction perpendicular to the second main surface; a gate groove extending from the second main surface in the perpendicular direction and penetrating the source region and the well region in a direction parallel to the first main surface of the substrate; and a gate electrode formed on a surface of the gate groove with a gate insulating film interposed therebetween, wherein the drift region has a higher impurity concentration than the substrate, and the well region extends to the inside of the substrate.

A semiconductor device includes a drift zone formed in a semiconductor portion. In a transition section of the semiconductor portion a vertical extension of the semiconductor portion decreases from a first vertical extension to a second vertical extension. A junction termination zone of a conductivity type complementary to a conductivity type of the drift zone is formed between a first surface of the semiconductor portion and the drift zone and includes a tapering portion in the transition section. In the tapering portion a vertical extension of the junction termination zone decreases from a maximum vertical extension to zero within a lateral width of at least twice the maximum vertical extension.

A method that is capable of preferably segmenting a substrate with a metal film. A method of segmenting a substrate with a metal film includes steps of: scribing a predetermined segment position in a first main surface on which a metal film is provided to form a scribe line and segmenting the metal film, and extending a vertical crack along the predetermined segment position toward an inner side of the substrate; and making a breaking bar have direct contact with the substrate with the metal film from a side of a second main surface on which the metal film is not provided to further extend the vertical crack, thereby segmenting the substrate with the metal film in the predetermined segment position.

A plurality of trenches are formed so as to reach a prescribed depth from the surface of an n-type epitaxial layer. A refractory metal carbide film, such as a TaC film is formed via sputtering on the surface of sections (mesa regions) of the n-type epitaxial layer interposed between the adjacent trenches. Sections of the TaC film on the inner walls of the trenches are removed via etching. While the surface of the mesa regions is covered by the TaC film, the inside of the trenches is filled with a p-type epitaxial layer that is grown by CVD, thereby forming a parallel pn structure. Then, sections of the p-type epitaxial layer protruding above the surface of the parallel pn structure and the TaC film above the surface of the mesa regions are ground until top surfaces of n-type regions and p-type regions of the parallel pn structure are exposed.

A silicon carbide semiconductor device includes an n-type silicon carbide semiconductor substrate, a drain electrode electrically connected to a rear face, an n-type semiconductor layer having a second impurity concentration lower than the first impurity concentration, a p-type first semiconductor region, an n-type second semiconductor region, and an n-type third semiconductor region. A trench is formed having a gate electrode therein in which the bottom face of the trench contacts the p-type semiconductor region. A metal layer is electrically connected to the third semiconductor region, and a source electrode electrically connects the second semiconductor region and the metal layer to each other.