Semiconductor substrate thinning systems and methods. Implementations of a method of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface and inducing damage into a portion of the semiconductor substrate adjacent to the second surface forming a damage layer. The method may also include backgrinding the second surface of the semiconductor substrate.

An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.

A planarization method includes a grinding step of holding the opposite side to a separation surface in an SiC ingot by a rotatable chuck table and rotating a grinding wheel having plural grinding abrasives disposed in a ring manner to grind the separation surface of the SiC ingot held by the chuck table, and a flatness detection step of irradiating the separation surface of the SiC ingot exposed from the grinding wheel with light and detecting reflected light to detect the degree of flatness. The grinding step is ended when that the separation surface of the SiC ingot has become flat is detected in the flatness detection step.

A silicon carbide semiconductor device includes: a vertical semiconductor element, which includes: a semiconductor substrate made of silicon carbide and having a high impurity concentration layer on a back side and a drift layer on a front side; a base region made of silicon carbide on the drift layer; a source region arranged on the base region and made of silicon carbide; a deep layer disposed deeper than the base region; a trench gate structure including a gate insulation film arranged on an inner wall of a gate trench which is arranged deeper than the base region and shallower than the deep layer, and a gate electrode disposed on the gate insulation film; a source electrode electrically connected to the base region, the source region, and the deep layer; and a drain electrode electrically connected to the high impurity concentration layer.

A method for manufacturing a silicon carbide substrate includes steps of preparing a silicon carbide substrate having a main surface, polishing the main surface of the silicon carbide substrate using a polishing agent containing a metal catalyst, and cleaning the silicon carbide substrate after the step of polishing. The step of cleaning includes a step of cleaning the silicon carbide substrate with aqua regia.

A method for manufacturing a semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, including forming a second conductive-type SiC base layer on a substrate, and selectively implanting first and second conductive-type impurities into surfaces of the substrate and base layer to form a collector region, a channel region in a surficial portion of the SiC base layer, and an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET.

A method for fabricating an optical element is provided. The fabrication method includes the following steps. A substrate is provided. A plurality of metal grids are formed on the substrate. A first organic layer is formed on the substrate between the plurality of metal grids. A second organic layer is formed on the first organic layer and the plurality of metal grids. The second organic layer and the first organic layer are etched to leave the plurality of metal grids and a plurality of patterned second organic layers on the plurality of metal grids. An optical element fabricated by the method is also provided.

An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.

A semiconductor wafer having a main surface and a rear surface opposite from the main surface is provided. A die singulation preparation step is performed in kerf regions of the semiconductor wafer. The kerf regions enclose a plurality of die sites. The die singulation preparation step includes forming one or more preliminary kerf trenches between at least two immediately adjacent die sites. The method further includes forming active semiconductor devices in the die sites, and singulating the semiconductor wafer in the kerf regions thereby providing a plurality of discrete semiconductor dies from the die sites. The one or more preliminary kerf trenches are unfilled during the singulating, and the singulating includes removing semiconductor material from a surface of the semiconductor wafer that is between opposite facing sidewalls of the one or more preliminary kerf trenches.

A semiconductor device according to the present invention includes a substrate having a cell portion and a terminal portion surrounding the cell portion, a surface structure provided on the substrate, and a back surface electrode provided on the back surface of the substrate, the surface structure includes a convex portion protruding upward above the cell portion, and at least a part of the cell portion is thinner than the terminal portion.