A heat treatment container (1) is provided with support members (6) for supporting a disc-shaped SiC substrate (2), which is an object, at a time of an etching treatment of the SiC substrate (2). Each of the support members (6) has an inclined surface (6F) for supporting a lower surface end (2E) of the SiC substrate (2), the inclined surface being inclined so as to increasingly approach the centerline of the SiC substrate (2) going downward. More specifically, each of the support members (6) is formed in a conical shape with a diameter that increases going downward, and a conical surface which is the peripheral surface of each supporting member forms the inclined surface (6F). A vertically-middle section of the inclined surface (6F) contacts the lower surface end (2E) of the SiC substrate (2).

An object of the present invention is to provide a novel technique for evaluating a heat treatment environment. The present invention is a method for evaluating a heat treatment environment, the method comprising an image acquisition step of acquiring an image by making an electron beam incident at an incident angle inclined with respect to a normal line of a {0001} plane of a heat-treated silicon carbide substrate and an environment evaluation step of evaluating a heat treatment environment of the silicon carbide substrate on a basis of on contrast information of the image.

A method of forming concurrently openings in a substrate or wafer or a portion of substrate or wafer openings therein at least one of the openings has a relatively high aspect ratio and another one of the openings has a relatively low aspect ratio, the method comprising: bonding the substrate or wafer or a portion of substrate or wafer to a carrier substrate; forming a ring trench in the substrate or wafer or in a portion of the substrate or wafer, the ring trench having an outer perimeter that corresponds an outer perimeter of the another one of the openings having said relatively low aspect ratio and having an inner perimeter spaced from the outer perimeter by a predetermined distance; forming an opening in said substrate or wafer or in a portion of substrate or wafer having said high aspect ratio concurrently with the forming of the ring trench; and separating the substrate or wafer or in a portion of the substrate or wafer from the carrier substrate.

A method of structuring and/or thinning a semiconductor wafer having a plurality of functional chip sites includes forming one or more semiconductor devices in a device region of each functional chip site at a frontside of the semiconductor wafer, and forming an electrode at one of the frontside or a backside of the semiconductor wafer. The side of the semiconductor wafer at which the electrode is formed is structured by applying voltage pulses between the electrode and a tool electrode positioned above the semiconductor wafer as part of an electrical discharge machining (EDM) process before the electrode is removed by the EDM process, and between the tool electrode and an intrinsic conductive layer formed on the side of the semiconductor wafer being structured after the electrode is removed by the EDM process.

A semiconductor wafer having a main surface and a rear surface opposite from the main surface is provided. A die singulation preparation step is performed in kerf regions of the semiconductor wafer. The kerf regions enclose a plurality of die sites. The die singulation preparation step includes forming one or more preliminary kerf trenches between at least two immediately adjacent die sites. The method further includes forming active semiconductor devices in the die sites, and singulating the semiconductor wafer in the kerf regions thereby providing a plurality of discrete semiconductor dies from the die sites. The one or more preliminary kerf trenches are unfilled during the singulating, and the singulating includes removing semiconductor material from a surface of the semiconductor wafer that is between opposite facing sidewalls of the one or more preliminary kerf trenches.

A gate connection layer (14) includes a portion placed on an outer trench (TO) with a gate insulating film (7) being interposed. A first main electrode (10) includes a main contact (CS) electrically connected to a well region (4) and a first impurity region (5) within an active region (30), and an outer contact (CO) being spaced away from the active region (30) and in contact with a bottom face of the outer trench (TO). A trench-bottom field relaxing region (13) is provided in a drift layer (3). A trench-bottom high-concentration region (18) has an impurity concentration higher than that of the trench-bottom field relaxing region (13), is provided on the trench-bottom field relaxing region (13), and extends from a position where it faces the gate connection layer (14) with the gate insulating film (7) being interposed, to a position where it is in contact with the outer contact (CO) of the first main electrode (10).

A system and method for fabricating an orifice in a multi-layered semiconductor substrate and singulation of the semiconductor substrate includes adding a sacrificial layer of material to a first surface of a semiconductor substrate; subsequently, removing a first radius of a first depth of material from the semiconductor substrate along a direction normal to the first surface, the removal of the first depth of material uses a first removal technique that removes the first depth of material; and removing a second radius of a second depth of material from the semiconductor substrate along the direction normal to the first surface based on the removal of the first depth of material, the removal of the second depth of material uses a second removal technique.

A system and method for fabricating an orifice in a multi-layered semiconductor substrate and singulation of the semiconductor substrate includes adding a sacrificial layer of material to a first surface of a semiconductor substrate; subsequently, removing a first radius of a first depth of material from the semiconductor substrate along a direction normal to the first surface, the removal of the first depth of material uses a first removal technique that removes the first depth of material; and removing a second radius of a second depth of material from the semiconductor substrate along the direction normal to the first surface based on the removal of the first depth of material, the removal of the second depth of material uses a second removal technique.

A power semiconductor device includes a silicon carbide substrate and at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The device includes a stop layer that is disposed at least in part laterally between the pits. The device further comprising an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts, wherein the ohmic metal contacts at least parts of the stop layer.

A silicon carbide chip array containing a silicon carbide substrate; a silicon carbide layer on top of the silicon carbide substrate; a first metal contact connected to the silicon carbide substrate; and two second metal contacts connected to the first portion and the second portion respectively. The silicon carbide layer is thinner and having lower doping than the silicon carbide layer. The silicon carbide layer includes a first portion and a second portion which are separate from each other. Each one of the second metal contacts forms a semiconductor device with the first metal contact. At least one of the first and second portions contains a side face which is inclined with respect to the silicon carbide substrate. Such a configuration enhances the breakdown voltage and reduces leakage current of the resultant silicon carbide diode array.