The technology of this application relates to a silicon carbide substrate, a silicon carbide device, and a substrate thinning method thereof. The method includes: providing a first substrate, where the first substrate is a silicon carbide substrate, and the first substrate has a silicon surface and a carbon surface that are opposite to each other; forming a silicon carbide device on the silicon surface of the first substrate, and forming a protective layer on the silicon carbide device; performing ion implantation on the carbon surface of the first substrate; providing a second substrate; bonding an ion-implanted first substrate to the second substrate; performing high-temperature annealing on the bonded first substrate and the second substrate to combine ions implanted into the first substrate into gas; and performing separation at a position of ion implantation of the first substrate to obtain a thinned first substrate and a separated first substrate.

A SiC SJ trench MOSFET having first and second type gate trenches for formation of gate electrodes and super junction regions is disclosed. The gate electrodes are disposed into the first type gate trenches having a thick oxide layer on trench bottom. The super junction regions are formed surrounding the second type gate trenches filled up with the thick oxide layer. The device further comprises gate oxide electric field reducing regions adjoining lower surfaces of body regions and space apart from the gate trenches.

A semiconductor device of an embodiment includes a silicon carbide layer having first and second plane, the silicon carbide layer including trench having a first portion and a second portion, the second portion having a width smaller than the first portion, an n-type first silicon carbide region, a p-type second silicon carbide region between the first silicon carbide region and the first plane, a p-type third silicon carbide region between the second silicon carbide region and the first plane and having a p-type impurity concentration lower than the second silicon carbide region, an n-type fourth silicon carbide region between the third silicon carbide region and the first plane, and an n-type fifth silicon carbide region between the second portion and the second silicon carbide region and having an n-type impurity concentration higher than the first silicon carbide region; and a gate electrode in the trench.

A silicon carbide semiconductor device includes a silicon carbide (SiC) substrate having a SiC epitaxial layer disposed over a surface of the SiC substrate, the SiC substrate having a first conductivity and the SiC epitaxial layer having the first conductivity. A contact region and a well region are formed in the SiC epitaxial layer, the contact region and the well region have a doping level of a second conductivity opposite the first conductivity. The contact region lies completely within the well region, is not in contact with a region having the first conductivity and has edges recessed from edges of the well region.

A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.

A wafer having a first surface, an opposite second surface, and an outer circumferential surface that includes a curved part curved outward in a protruding manner is separated into two wafers. Part of the wafer is removed along the curved part, and a separation origin is formed inside the wafer by positioning the focal point of a laser beam with a wavelength having transmissibility with respect to the wafer inside the wafer and executing irradiation with the laser beam while the focal point and the wafer are relatively moved in such a manner that the focal point is kept inside the wafer. The wafer is separated into two wafers by an external force.

An electrical discharge machining system includes a semiconductor workpiece, a voltage source, an EDM tool, and an illumination system. The illumination system is configured to illuminate the semiconductor workpiece in order to increase the conductivity of the semiconductor workpiece. The voltage source establishes an electric potential difference between the workpiece and the EDM tool while the illumination system illuminates the semiconductor workpiece. The electric potential difference is such that an electrical discharge occurs between the workpiece and the EDM tool, thereby removing material from the workpiece.

A selectivity can be improved in a desirable manner when etching a processing target object containing silicon carbide. An etching method of processing the processing target object, having a first region containing silicon carbide and a second region containing silicon nitride and in contact with the first region, includes etching the first region to remove the first region atomic layer by atomic layer by repeating a sequence comprising: generating plasma from a first gas containing nitrogen to form a mixed layer containing ions contained in the plasma generated from the first gas in an atomic layer of an exposed surface of the first region; and generating plasma from a second gas containing fluorine to remove the mixed layer by radicals contained in the plasma generated from the second gas.

A method of forming a semiconductor device includes forming a trench in a semiconductor body; at least partially filling the trench with a filling material, the filling material; introducing dopants into a portion of the filling material, where the dopants have a first diffusion coefficient relative to the filling material and have a second diffusion coefficient relative to the semiconductor body, where the first diffusion coefficient is greater than the second diffusion coefficient, and where a ratio of the first diffusion coefficient to the second diffusion coefficient is greater than 10; and applying thermal processing to the semiconductor body configured to spread the dopants in the filling material along a vertical direction between a bottom side and a top side of the filling material by a diffusion process.

A method includes providing a layer of porous silicon carbide supported by a silicon carbide substrate, providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide, forming a plurality of semiconductor devices in the layer of epitaxial silicon carbide, and separating the substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. Additional methods are described.