An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

This semiconductor device includes: an n-type SiC drift layer; a p-type base region; an n-type source region selectively embedded in the top part of the base region; p-type base contact regions selectively embedded in the top part of the base region so as to form a first gap with the source region along the <11-20> direction; a gate electrode provided via a gate insulating film; and an n-type drain region. The top surface of the drain region has an off-angle relative to the <11-20> direction towards the <0001> direction, and an alignment mark for positioning is formed on the top surface. The drift layer and the base region are epitaxially grown films, and a width wg of the first gap is set in accordance with a positional deviation width of the alignment mark caused by the off-angle and epitaxial growth.

Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. Different thickness in an epi-growth scheme is adopted to create different sheet thicknesses within the same device channel regions for use in manufacturing vertically stacked nano structure (e.g., nanosheet, nanowire, or the like) GAA devices. A GAA device may be formed with a vertical stack of nanostructures in a channel region with a topmost nanostructure of the vertical stack being thicker than the other nanostructures of the vertical stack. Furthermore, an LDD portion of the topmost nano structure may be formed as the thickest of the nanostructures in the vertical stack.

A method includes providing a first layer of epitaxial silicon carbide supported by a silicon carbide substrate, providing a second layer of epitaxial silicon carbide on the first layer, forming a plurality of semiconductor devices in the second layer, and separating the substrate from the second layer at the first layer. The first layer includes a plurality of voids.

Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. Different thickness in an epi-growth scheme is adopted to create different sheet thicknesses within the same device channel regions for use in manufacturing vertically stacked nanostructure (e.g., nanosheet, nanowire, or the like) GAA devices. A GAA device may be formed with a vertical stack of nanostructures in a channel region with a topmost nanostructure of the vertical stack being thicker than the other nanostructures of the vertical stack. Furthermore, an LDD portion of the topmost nanostructure may be formed as the thickest of the nanostructures in the vertical stack.

This semiconductor device includes: an n-type SiC drift layer; a p-type base region; an n-type source region selectively embedded in the top part of the base region; p-type base contact regions selectively embedded in the top part of the base region so as to form a first gap with the source region along the <11-20> direction; a gate electrode provided via a gate insulating film; and an n-type drain region. The top surface of the drain region has an off-angle relative to the <11-20> direction towards the <0001> direction, and an alignment mark for positioning is formed on the top surface. The drift layer and the base region are epitaxially grown films, and a width wg of the first gap is set in accordance with a positional deviation width of the alignment mark caused by the off-angle and epitaxial growth.

A gap-fill polymer for filling fine pattern gaps, which has a low dielectric constant (low-k) and excellent gap filling properties, may consist of a compound formed by condensation polymerization of a first oligomer represented by the formula 1 and a second oligomer represented by the formula 2.

A method for manufacturing a wide bandgap junction barrier Schottky diode having an anode side and a cathode side is provided, wherein an (n+) doped cathode layer is arranged on the cathode side, at least on p doped anode layer is arranged on the anode side, an (n) doped drift layer is arranged between the cathode layer and the at least one anode layer, which drift layer extends to the anode side, wherein the following manufacturing steps are performed: a) providing an (n+) doped wide bandgap substrate, b) creating the drift layer on the cathode layer, c) creating the at least one anode layer on the drift layer, d) applying a first metal layer on the anode side on top of the drift layer for forming a Schottky contact, characterized in, that e) creating a second metal layer on top of at least one anode layer, wherein after having created the first and the second metal layer, a metal layer on top of the at least one anode layer has a second thickness and a metal layer on top of the drift layer has a first thickness, wherein the second thickness is smaller than the first thickness, f) then performing a first heating step at a first temperature, by which due the second thickness being smaller than the first thickness an ohmic contact is formed at the interface between the second metal layer and the at least one anode layer, wherein performing the first heating step such that a temperature below the first metal layer is kept below a temperature for forming an ohmic contact.

A gap-fill polymer for filling fine pattern gaps, which has a low dielectric constant (flow-k) and excellent gap filling properties may consist of a compound formed by condensation polymerization of a first oligomer represented by the formula 1 and a second oligomer represented by the formula 2.

An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.