A display substrate includes: a base substrate; a switching device disposed on the base substrate, the switching device including a gate electrode, a source electrode, and a drain electrode overlapping at least a part of the gate electrode; a wavelength converting layer disposed on the switching device, the wavelength converting layer including a quantum dot; a bridge electrode disposed on the wavelength converting layer, the bridge electrode electrically connected to the drain electrode through a first contact hole formed through the wavelength converting layer; a planarizing layer disposed on the wavelength converting layer; and a pixel electrode disposed on the planarizing layer, the pixel electrode electrically connected to the bridge electrode through a second contact hole formed through the planarizing layer.

An array substrate and a method for manufacturing the same, and a display device are provided. The method includes: forming a thin film transistor (TFT) structure of a display region and a TFT structure of the GOA region on a substrate; sequentially forming a first insulating layer, an indium tin oxide (ITO) layer and a photoresist layer on the TFT structure; exposing and developing the photoresist layer using a halftone mask plate, and etching the ITO layer, to form an electrode layer in the GOA region and an electrode layer in the display region; and ashing the remaining photoresist to completely remove the photoresist on the electrode layer in the display region and to thinning the photoresist on the electrode layer in the GOA region.

An array substrate and a method for manufacturing the same, and a display device are provided. The method includes: forming a thin film transistor (TFT) structure of a display region and a TFT structure of the GOA region on a substrate; sequentially forming a first insulating layer, an indium tin oxide (ITO) layer and a photoresist layer on the TFT structure; exposing and developing the photoresist layer using a halftone mask plate, and etching the ITO layer, to form an electrode layer in the GOA region and an electrode layer in the display region; and ashing the remaining photoresist to completely remove the photoresist on the electrode layer in the display region and to thinning the photoresist on the electrode layer in the GOA region.

A semiconductor element is disclosed including a construction with electrode-dividing grooves, in which a dark current is smaller than in existing examples. A method of forming such grooves is also disclosed. In an embodiment, grooves, which electrically divide an electrode layer formed on the surface of a substrate, are formed with a V-shaped cross-sectional shape, groove side walls in the electrode layer, constituting the grooves, being sloping surfaces. An embodiment of the method of forming the grooves includes using a dicing blade having a blade distal end portion which is sharpened into a V-shape to cut a semiconductor wafer in which multiple patterns of semiconductor elements including an electrode layer on the surface of a substrate are formed, forming the grooves having a V-shaped cross-sectional shape which divide the electrode layer in each semiconductor element.

The present disclosure provides a touch panel, a manufacturing method thereof and a touch display device. In one embodiment, the method comprises the following steps: 1) forming touch lines, comprising: forming in the same layer gate lines and a plurality of first touch lines, each first touch line being arranged intermittently in a direction of data lines and not electrically connected with the gate lines, and forming in the same layer a plurality of first connection lines and electrodes which are not in the same layer as the gate lines and the touch electrodes, each first connection line being used for connecting in series with an intermittent first touch line, each touch line comprising a first touch line and a plurality of first connection lines; and 2) forming touch electrodes, each touch electrode being electrically connected with one or more first touch lines, one or more is second touch lines, or one or more third touch lines. Accordingly, the manufacturing process steps of a self-capacitance in-cell touch panel can be reduced and the process can be simplified.

This adhesive contains an epoxy compound, a cationic catalyst, and an acrylic resin that includes acrylic acid and an acrylic acid ester having a hydroxyl group. The acrylic acid in the acrylic resin reacts with the epoxy compound, creating a link between the acrylic resin island part and the epoxy compound sea part, and strengthening the anchoring effect with respect to the epoxy compound sea part by roughening the surface of an oxide film. Furthermore, the hydroxyl-group-containing acrylic acid ester in the acrylic resin becomes electrostatically adhesive to wiring due to the polarity of the hydroxyl group. Excellent adhesive strength can be obtained by adhering, in this way, the entire cured product composed of the acrylic resin island part and the epoxy compound sea part to the oxide film.

The present disclosure provides a touch panel, a manufacturing method thereof and a touch display device. The method comprises: 1) forming touch lines, comprising: forming in the same layer gate lines and a plurality of first touch lines, each first touch line being arranged intermittently in a direction of data lines and not electrically connected with the gate lines, and forming in the same layer a plurality of first connection lines and electrodes not in the same layer as the gate lines and the touch electrodes, each first connection line being used for connecting in series with an intermittent first touch line, each touch line comprising a first touch line and a plurality of first connection lines; and 2) forming touch electrodes, each touch electrode being electrically connected with one or more first touch lines, one or more second touch lines, or one or more third touch lines.

An array substrate and a method for manufacturing the same, and a display device are provided. The method includes: forming a thin film transistor (TFT) structure of a display region and a TFT structure of the GOA region on a substrate; sequentially forming a first insulating layer, an indium tin oxide (ITO) layer and a photoresist layer on the TFT structure; exposing and developing the photoresist layer using a halftone mask plate, and etching the ITO layer, to form an electrode layer in the GOA region and an electrode layer in the display region; and ashing the remaining photoresist to completely remove the photoresist on the electrode layer in the display region and to thinning the photoresist on the electrode layer in the GOA region.

An array substrate and a method for manufacturing the same, and a display device are provided. The method includes: forming a thin film transistor (TFT) structure of a display region and a TFT structure of the GOA region on a substrate; sequentially forming a first insulating layer, an indium tin oxide (ITO) layer and a photoresist layer on the TFT structure; exposing and developing the photoresist layer using a halftone mask plate, and etching the ITO layer, to form an electrode layer in the GOA region and an electrode layer in the display region; and ashing the remaining photoresist to completely remove the photoresist on the electrode layer in the display region and to thinning the photoresist on the electrode layer in the GOA region.

Implementations described herein generally relate to methods for leveling a component above a substrate. In one implementation, a test substrate is placed on a substrate support inside of a processing chamber. A component, such as a mask, is located above the substrate. The component is lowered to a position so that the component and the substrate are in contact. The component is then lifted and the particle distribution on the test substrate is reviewed. Based on the particle distribution, the component may be adjusted. A new test substrate is placed on the substrate support inside of the processing chamber, and the component is lowered to a position so that the component and the new test substrate are in contact. The particle distribution on the new test substrate is reviewed. The process may be repeated until a uniform particle distribution is shown on a test substrate.