An electronic apparatus is provided and includes a first substrate comprising a first conductive layer; a second substrate which is opposed to the first conductive layer and is separated from the first conductive layer, the second substrate including a second conductive layer, and a first hole penetrating the second substrate; and a connecting material which electrically connects the first conductive layer and the second conductive layer via the first hole, wherein the connecting material consists of a single material; and the second conductive layer is located on the second substrate on a side opposite to a side that is opposed to the first conductive layer.

A fabrication method for a semiconductor device includes measuring a thickness of a semiconductor substrate in which a bulk donor of a first conductivity type is entirely distributed, adjusting an implantation condition in accordance with the thickness of the semiconductor substrate and implanting hydrogen ions from a lower surface of the semiconductor substrate to an upper surface side of the semiconductor substrate, and annealing the semiconductor substrate and forming, in a passage region through which the hydrogen ions have passed, a first high concentration region of the first conductivity type in which a donor concentration is higher than a doping concentration of the bulk donor.

Techniques for tight pitch patterning are provided. In one aspect, a patterning method includes: forming mandrels on a substrate; forming spacers that are undoped alongside the mandrels, wherein gaps are present between the spacers; filling the gaps with a sacrificial material having a dopant; forming a mask having an opening marking a cut region of at least one of the spacers; removing the sacrificial material from the cut region of the at least one spacer via the mask; removing the mask; performing an anneal to diffuse the dopant from the sacrificial material into the spacers to form doped spacers, wherein following the anneal the cut region of the at least one spacer remains undoped; removing the cut region of the at least one spacer selective to the doped spacers; and patterning features in the substrate using the doped spacers as a hardmask. A patterning structure is also provided.

The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide.

A method for forming a semiconductor structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes depositing a dopant source layer over the gate structure. The method also includes driving dopants of the dopant source layer into the fin structure. The method also includes removing the dopant source layer. The method also includes annealing the dopants in the fin structure to form a doped region. The method also includes etching the doped region and the fin structure below the doped region to form a recess. The method also includes growing a source/drain feature in the recess.

A silicon carbide semiconductor device includes an n-type drift layer disposed on an n-type silicon carbide substrate; an n-type current spreading layer disposed on a top surface of the drift layer, having a higher impurity concentration than the drift layer; a p-type base region disposed on a top surface of the current spreading layer; a p-type gate-bottom protection region located in the current spreading layer; a p-type base-bottom embedded region located in the current spreading layer, separated from the gate-bottom protection region to be in contact with a bottom surface of the base region; an insulated-gate electrode structure disposed in a trench penetrating the base region to reach the gate-bottom protection region, and a lower recombination region disposed in a lower portion of the drift layer, including crystal defects configured to recombine minority carriers injected into the drift layer.

A method of doping a substrate. The method may include providing a substrate in a process chamber. The substrate may include a semiconductor structure, and a dopant layer disposed on a surface of the semiconductor structure. The method may include maintaining the substrate at a first temperature for a first interval, the first temperature corresponding to a vaporization temperature of the dopant layer. The method may further include rapidly cooling the substrate to a second temperature, less than the first temperature, and heating the substrate from the second temperature to a third temperature, greater than the first temperature.

A method of doping a substrate. The method may include providing a substrate in a process chamber. The substrate may include a semiconductor structure, and a dopant layer disposed on a surface of the semiconductor structure. The method may include maintaining the substrate at a first temperature for a first interval, the first temperature corresponding to a vaporization temperature of the dopant layer. The method may further include rapidly cooling the substrate to a second temperature, less than the first temperature, and heating the substrate from the second temperature to a third temperature, greater than the first temperature.

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a diffusion blocking layer on a semiconductor substrate; forming channel material layers over the diffusion blocking layer; patterning the semiconductor substrate, the channel material layers, and the diffusion blocking layer to form a trench in the semiconductor substrate, thereby defining an active region being adjacent the trench; filling the trench with a dielectric material layer and a solid doping source material layer containing a dopant; and driving the dopant from the solid doping source material layer to the active region, thereby forming an anti-punch-through (APT) feature in the active region.

Provided is a semiconductor device provided with an IGBT, comprising: a semiconductor substrate having upper and lower surfaces, throughout which bulk donors are distributed; a hydrogen peak including a local maximum arranged 25 μm or more away from the lower surface of the semiconductor substrate in a depth direction, at which a hydrogen chemical concentration shows a local maximum value; an upper tail where the hydrogen chemical concentration decreases in a direction from the local maximum toward the upper surface; and a lower tail where the hydrogen chemical concentration decreases in a direction from the local maximum toward the lower surface more gradually than the upper tail; and a first high concentration region having a donor concentration higher than a bulk donor concentration and including a region extending for 4 μm or more in a direction from the local maximum of the hydrogen peak toward the upper surface.