Embodiments of the present invention are directed to a semiconductor structure and a method for forming a semiconductor structure having a self-aligned dielectric pillar for reducing trench silicide-to-gate parasitic capacitance. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. A dielectric pillar is positioned adjacent to the nanosheet stack and on a shallow trench isolation region of the substrate. The nanosheet stack is recessed to expose a surface of the shallow trench isolation region and a source or drain (S/D) region is formed on the exposed surface of the shallow trench isolation region. A contact trench is formed that exposes a surface of the S/D region and a surface of the dielectric pillar.

Embodiments of the present invention are directed to a semiconductor structure and a method for forming a semiconductor structure having a self-aligned dielectric pillar for reducing trench silicide-to-gate parasitic capacitance. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. A dielectric pillar is positioned adjacent to the nanosheet stack and on a shallow trench isolation region of the substrate. The nanosheet stack is recessed to expose a surface of the shallow trench isolation region and a source or drain (S/D) region is formed on the exposed surface of the shallow trench isolation region. A contact trench is formed that exposes a surface of the S/D region and a surface of the dielectric pillar.

A method may include providing a substrate having a surface that defines a substrate plane and a substrate feature that extends from the substrate plane; directing an ion beam comprising angled ions to the substrate at a non-zero angle with respect to a perpendicular to the substrate plane, wherein a first portion of the substrate feature is exposed to the ion beam and wherein a second portion of the substrate feature is not exposed to the ion beam; directing molecules of a molecular species to the substrate wherein the molecules of the molecular species cover the substrate feature; and providing a second species to react with the molecular species, wherein selective growth of a layer comprising the molecular species and the second species takes place such that a first thickness of the layer grown on the first portion is different from a second thickness grown on the second portion.

A method comprises depositing a mask layer on a front-side surface of a wafer, wherein a portion of the wafer has a first resistivity; with the mask layer in place, performing an ion implantation process on a backside surface of the wafer to implant a resistivity reduction impurity into the wafer through the backside surface of the wafer to lower the first resistivity of the portion of the wafer to a second resistivity; after performing the ion implantation process, removing the mask layer from the front-side surface of the wafer; and forming semiconductor devices on the front-side surface of the wafer.

A method comprises depositing a mask layer on a front-side surface of a wafer, wherein a portion of the wafer has a first resistivity; with the mask layer in place, performing an ion implantation process on a backside surface of the wafer to implant a resistivity reduction impurity into the wafer through the backside surface of the wafer to lower the first resistivity of the portion of the wafer to a second resistivity; after performing the ion implantation process, removing the mask layer from the front-side surface of the wafer; and forming semiconductor devices on the front-side surface of the wafer.

There may be provided a method for inspecting a top redistribution layer conductors of an object. The top redistribution layer (RDL) is positioned above at least one lower RDL and above at least one other dielectric layer. The method may include (i) illuminating the object with radiation, the at least one lower dielectric layer significantly absorbs the radiation; (ii) generating, by a detector, detection signals that represent radiation reflected from the object, and (iii) processing, by a processor, the detection signal to provide information about the top RDL. The processing may include distinguishing detection signals related to the top RDL from detection signals related to the at least one lower RDL.

There may be provided a method for inspecting a top redistribution layer conductors of an object. The top redistribution layer (RDL) is positioned above at least one lower RDL and above at least one other dielectric layer. The method may include (i) illuminating the object with radiation, the at least one lower dielectric layer significantly absorbs the radiation; (ii) generating, by a detector, detection signals that represent radiation reflected from the object, and (iii) processing, by a processor, the detection signal to provide information about the top RDL. The processing may include distinguishing detection signals related to the top RDL from detection signals related to the at least one lower RDL.

The present invention is a method for manufacturing a substrate for a solar cell composed of a single crystal silicon, including the steps of: producing a silicon single crystal ingot; slicing a silicon substrate from the silicon single crystal ingot; and subjecting the silicon substrate to low temperature thermal treatment at a temperature of 800° C. or more and less than 1200° C., wherein the silicon single crystal ingot or the silicon substrate is subjected to high temperature thermal treatment at a temperature of 1200° C. or more for 30 seconds or more before the low temperature thermal treatment. As a result, it is possible to provide a method for manufacturing a substrate for a solar cell that can prevent decrease in the minority carrier lifetime of the substrate even when the substrate has higher oxygen concentration.

In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.

In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.