A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-doped layer is formed on the p-doped layer, the n-doped layer including a doped III-V material. A contact interface layer is formed on the n-doped layer. The contact interface layer includes a II-VI material. A contact metal is formed on the contact interface layer to form an electronic device.

In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.

The present disclosure relates to the technical field of semiconductors. Disclosed is a multi-layer semiconductor material structure and a preparation method thereof, solving the problems of the existing semiconductor materials that have poor heat dissipation, high cost, and cannot be mass-produced. The multi-layer semiconductor material structure includes a highly thermally conductive support substrate and a crystallized device function layer, where the device function layer is provided on the highly thermally conductive support substrate, and has a single-crystal surface layer.

In one aspect, a transistor comprises a metal emitter, a first semiconductor barrier, a metal base, a second semiconductor barrier, and a metal collector. The first semiconductor barrier separates the metal emitter and the metal base and has an average thickness based on a first mean free path of a charge carrier in the first semiconductor barrier emitted from the metal emitter. The second semiconductor barrier separates the metal base from the metal collector and has an average thickness based on a second mean free path of the charge carrier in the second semiconductor barrier injected from the metal base. The metal base comprises two or more metal layers and has an average thickness based on a multi-layer mean free path of the charge carrier.

In one aspect, a transistor comprises a metal emitter, a first semiconductor barrier, a metal base, a second semiconductor barrier, and a metal collector. The first semiconductor barrier separates the metal emitter and the metal base and has an average thickness based on a first mean free path of a charge carrier in the first semiconductor barrier emitted from the metal emitter. The second semiconductor barrier separates the metal base from the metal collector and has an average thickness based on a second mean free path of the charge carrier in the second semiconductor barrier injected from the metal base. The metal base comprises two or more metal layers and has an average thickness based on a multi-layer mean free path of the charge carrier.

A GaN-based compound semiconductor device includes a GaN-based epitaxial structure and an annealed metal layered structure that is formed on the GaN-based epitaxial structure. The annealed metal layered structure includes a metallic barrier layer, a conductive unit, and a protective unit which is formed on a lateral surface of the conductive unit. The metallic barrier layer and the conductive unit are sequentially disposed on the GaN-based epitaxial structure in such order. An ohmic contact is formed between the GaN-based epitaxial structure and the annealed metal layered structure. The protective unit includes a metal oxide material having one of NiAlO, AuAlO, and a combination thereof.