Patent classifications
H01L21/24
Shallow angle, multi-wavelength, multi-receiver, adjustable sensitivity aligner sensor for semiconductor manufacturing equipment
A workpiece alignment system is provided has a light emission apparatus that directs a light beam at a plurality of wavelengths along a path at a shallow angle toward a first side of a workpiece plane at a peripheral region. A light receiver apparatus, receives the light beam on a second side opposite the first side. A rotation device selectively rotates a workpiece support. According controller determines a position of the workpiece based on an amount of the light beam received through the workpiece when the workpiece intersects the path. A sensitivity of the light receiver apparatus is controlled based on a transmissivity of the workpiece. A position of the workpiece is determined when the workpiece is rotated based on the rotational position, an amount of the light beam received, the transmissivity of the workpiece, detection of a workpiece edge, and the controlled sensitivity of the light receiver apparatus.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device may include: exposing a surface of a gallium oxide substrate to an acidic or alkaline chemical solution so as to increase a surface roughness of the surface; and forming an electrode on the surface having the increased surface roughness.
Automated network-based test system for set top box devices
An automated network-based test system for set top box devices is disclosed. According to certain embodiments, the network-based testing system using Simple Network Management Protocol facilitates remote testing of thousands of set-top boxes, where groups of these set top boxes can be located in various locations that are remote from a main controller server that is running the tests remotely.
Contact formation through low-temperature epitaxial deposition in semiconductor devices
A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.
Localized tunneling enhancement for semiconductor devices
A semiconductor device includes a plurality of base layers. A tunneling layer is disposed on the plurality of base layers. A contact layer is disposed on the tunneling layer. An alloyed metal contact is annealed on to the contact layer. The alloyed metal contact forms a first region and a second region in the contact layer. The first region of the contact layer diffuses into the tunneling layer. The second region of the contact layer resides over the tunneling layer. The tunneling layer facilitates electron mobility of the second region.
Localized tunneling enhancement for semiconductor devices
A semiconductor device includes a plurality of base layers. A tunneling layer is disposed on the plurality of base layers. A contact layer is disposed on the tunneling layer. An alloyed metal contact is annealed on to the contact layer. The alloyed metal contact forms a first region and a second region in the contact layer. The first region of the contact layer diffuses into the tunneling layer. The second region of the contact layer resides over the tunneling layer. The tunneling layer facilitates electron mobility of the second region.
Laser doping apparatus and laser doping method
The laser doping apparatus may irradiate a predetermined region of a semiconductor material with a pulse laser beam to perform doping. The laser doping apparatus may include: a solution supplying system configured to supply dopant-containing solution to the predetermined region, and a laser system including at least one laser device configured to output the pulse laser beam to be transmitted by the dopant-containing solution, and a time-domain pulse waveform changing apparatus configured to control a time-domain pulse waveform of the pulse laser beam.
WAFER-LEVEL PACKAGING METHOD AND PACKAGE STRUCTURE THEREOF
Wafer-level packaging method and package structure are provided. In an exemplary method, first chips are bonded to the device wafer. A first encapsulation layer is formed on the device wafer, covering the first chips. The first chip includes: a chip front surface with a formed first pad, facing the device wafer; and a chip back surface opposite to the chip front surface. A first opening is formed in the first encapsulation layer to expose at least one first chip having an exposed chip back surface for receiving a loading signal. A metal layer structure is formed covering the at least one first chip, a bottom and sidewalls of the first opening, and the first encapsulation layer, followed by an alloying treatment on the chip back surface and the metal layer structure to form a back metal layer on the chip back surface.
PATTERNING PLATINUM BY ALLOYING AND ETCHING PLATINUM ALLOY
There is provided a method of patterning platinum on a substrate. A platinum layer is deposited on the substrate, and a patterned photoresist layer is formed over the platinum layer leaving partly exposed regions of the platinum layer. An aluminum layer is deposited over the partly exposed regions of the platinum layer. An alloy is formed of aluminum with platinum from the partly exposed regions. The platinum aluminum alloy is etched away leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate. In an embodiment, a thin hard mask layer is deposited on the platinum layer on the semiconductor substrate before the patterned photoresist layer is formed.
Method of manufacturing a semiconductor device having an undulated profile of net doping in a drift zone
A method of manufacturing a semiconductor device includes forming a profile of net doping in a drift zone of a semiconductor body by multiple irradiations with protons and generating hydrogen-related donors by annealing the semiconductor body. At least 50% of a vertical extension of the drift zone between first and second sides of the semiconductor body is undulated and includes multiple doping peak values between 110.sup.13 cm.sup.3 and 510.sup.14 cm.sup.3.