A semiconductor device in which parasitic capacitance is reduced is provided. A first insulating layer is deposited over a substrate. A first oxide insulating layer and an oxide semiconductor layer are deposited over the first insulating layer. A second oxide insulating layer is deposited over the oxide semiconductor layer and the first insulating layer. A second insulating layer and a first conductive layer are deposited over the second oxide insulating layer. A gate electrode layer, a gate insulating layer, and a third oxide insulating layer are formed by etching. A sidewall insulating layer including a region in contact with a side surface of the gate electrode layer is formed. A second conductive layer is deposited over the gate electrode layer, the sidewall insulating layer, the oxide semiconductor layer, and the first insulating layer. A third conductive layer is deposited over the second conductive layer. A low-resistance region is formed in the oxide semiconductor layer by performing heat treatment. An element contained in the second conductive layer moves from the second conductive layer to the oxide semiconductor layer side by performing the heat treatment. An element contained in the oxide semiconductor layer moves from the oxide semiconductor layer to the third conductive layer side by performing the heat treatment.

A method of manufacturing a semiconductor device includes forming a first metal layer on a semiconductor substrate and forming a second metal layer on the first metal layer. The second metal layer is formed of a different metal than the first metal layer. Microwave radiation is applied to the semiconductor substrate, first metal layer, and second metal layer to form an alloy comprising components of the first metal layer, second metal layer, and the semiconductor substrate.

Various methods and semiconductor structures for fabricating an FET device having Nickel atoms implanted in a silicide metal film on a source-drain contact region of the FET device thereby reducing resistance of the source-drain contact region of the FET device. An example fabrication method includes maskless blanket implantation of Nickel atoms across a semiconductor wafer. Nickel atoms can be implanted into silicide metal film of a source-drain contact region of nFET devices, pFET devices, or both, on a semiconductor wafer. Nickel atoms can be implanted into silicide metal film on a source-drain contact region of nFET devices and pFET devices. The silicide metal film on the source-drain contact region of the nFET device being a different material than the silicide metal film on the source-drain contact region of the pFET device.

Signal relay board for power semiconductor modules enabling electrical connection between power semiconductor modules and a drive unit driving same. A first wire layer, a second wire layer, a third wire layer, and a fourth wire layer of a multiphase wire portion are assigned with a first control wire layer serving as a path to provide a control signal to a first semiconductor device of the modules, a first ground wire layer serving as a path to provide a ground potential to a low potential side terminal of the first semiconductor device of the semiconductor modules, a second control wire layer serving as a path to provide a control signal to a second semiconductor device of the modules, and a second ground wire layer serving as a path to provide a ground potential to the second semiconductor device of the modules.

Signal relay board for power semiconductor modules enabling electrical connection between power semiconductor modules and a drive unit driving same. A first wire layer, a second wire layer, a third wire layer, and a fourth wire layer of a multiphase wire portion are assigned with a first control wire layer serving as a path to provide a control signal to a first semiconductor device of the modules, a first ground wire layer serving as a path to provide a ground potential to a low potential side terminal of the first semiconductor device of the semiconductor modules, a second control wire layer serving as a path to provide a control signal to a second semiconductor device of the modules, and a second ground wire layer serving as a path to provide a ground potential to the second semiconductor device of the modules.

The present disclosure generally relate to methods of processing a substrate in an epitaxy chamber. The method includes exposing a substrate having one or more fins to a group IV-containing precursor and a surfactant containing antimony to form an epitaxial film over sidewalls of the one or more fin structures, wherein the surfactant containing antimony is introduced into the epitaxy chamber before epitaxial growth of the epitaxial film, and a molar ratio of the surfactant containing antimony to the group IV-containing precursor is about 0.0001 to about 10.

A method for forming a semiconductor device comprises forming an insulation trench structure comprising insulation material extending into the semiconductor substrate from a surface of the semiconductor substrate. The insulation trench structure laterally surrounds a portion of the semiconductor substrate. The method further comprises modifying the laterally surrounded portion of the semiconductor substrate to form a vertical electrically conductive structure comprising an alloy material. The alloy material is an alloy of the semiconductor substrate material and at least one metal.

A method for forming a semiconductor device comprises forming an insulation trench structure comprising insulation material extending into the semiconductor substrate from a surface of the semiconductor substrate. The insulation trench structure laterally surrounds a portion of the semiconductor substrate. The method further comprises modifying the laterally surrounded portion of the semiconductor substrate to form a vertical electrically conductive structure comprising an alloy material. The alloy material is an alloy of the semiconductor substrate material and at least one metal.

Embodiments of the present disclosure include an image sensor device and methods of forming the same. An embodiment is an image sensor device including a first plurality of pickup regions in a photosensor array area of a substrate, each of first plurality of pickup regions having a first width and a first length, a second plurality of pickup regions in a periphery area of the substrate, the periphery area along at least one side of the photosensor array area, each of second plurality of pickup regions having a second width and a second length.

In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.