A semiconductor device includes source and a drain above a substrate and spaced apart along a first direction, and a semiconductor channel extending between the source and the drain. The semiconductor device further includes gate spacers, an interfacial layer, and a metal gate structure. The gate spacers are disposed on the semiconductor channel and spaced apart by a spacer-to-spacer distance along the first direction. The interfacial layer is on the semiconductor channel. The interfacial layer extends a length along the first direction, and the length is less than a minimum of the spacer-to-spacer distance along the first direction. The metal gate structure is over the interfacial layer.

A device includes a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure includes a first dielectric layer over the semiconductor channel, a first work function metal layer over the first dielectric layer, a first protection layer over the first work function metal layer, a second protection layer over the first protection layer, and a metal fill layer over the second protection layer.

A method of forming a semiconductor device includes forming a first layer over a substrate in a deposition chamber with a first deposition cycle and forming a second layer over the substrate in the deposition chamber with a second deposition cycle. The first deposition cycle includes flowing a first process gas over the substrate and flowing a second process gas over the substrate. The second deposition cycle includes flowing a third process gas over the substrate and flowing a fourth process gas over the substrate.

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure. The gate structure includes a gate dielectric layer, an n-type work function layer embedded in the gate dielectric layer, a dielectric capping layer embedded in the n-type work function layer, and a p-type work function layer embedded in the dielectric capping layer. A top surface of the gate structure exposes the n-type work function layer, the dielectric capping layer, and the p-type work function layer. The semiconductor structure also includes a first metal cap on the n-type work function layer and a second metal cap on the p-type work function layer. The first metal cap is spaced apart from the second metal cap. without formed on the dielectric capping layer.

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Two of the first tiers have different vertical thicknesses relative one another. Channel-material strings of memory cells extend through the first tiers and the second tiers. Through the horizontally-elongated trenches, first conductive material is formed in void space in the two first tiers. The first conductive material fills the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions. The first conductive material less-than-fills the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions. Through the horizontally-elongated trenches, the first conductive material is isotropically etched from the first tier having the larger vertical thickness in the individual memory-block regions to leave the first conductive material in the first tier having the smaller vertical thickness in the individual memory-block regions. After the isotropically etching of the first conductive material and through the horizontally-elongated trenches, second conductive material is formed in the first tier having the larger vertical thickness in the individual memory-block regions. Other embodiments, including structure independent of method, are disclosed.

A semiconductor memory device includes a substrate; a source diffusion region in the substrate; a pair of floating gates disposed on opposite of the source diffusion region; a first dielectric cap layer disposed directly on each of the floating gates; an erase gate disposed on the source diffusion region and partially overlapping an upper inner corner of each of the floating gates; a second dielectric cap layer disposed on the erase gate and the first dielectric cap layer; a select gate disposed on a sidewall of the first dielectric cap layer; and a drain diffusion region disposed in the substrate and adjacent to the select gate.

The disclosed technology generally relates to forming a thin film comprising titanium nitride (TiN), and more particularly to forming by a cyclical vapor deposition process the thin film comprising (TiN). In one aspect, a method of forming a thin film comprising TiN comprises exposing a semiconductor substrate to one or more first cyclical vapor deposition cycles each comprising an exposure to a first Ti precursor and an exposure to a first N precursor to form a first portion of the thin film and exposing the semiconductor substrate to one or more second cyclical vapor deposition cycles each comprising an exposure to a second Ti precursor and an exposure to a second N precursor to form a second portion of the thin film, wherein exposures to one or both of the first Ti precursor and the first N precursor during the one or more first cyclical vapor deposition cycles are at different pressures relative to corresponding exposures to one or both of the second Ti precursor and the second N precursor during the one or more second cyclical vapor deposition cycles. Aspects are also directed to semiconductor structures incorporating the thin film and method of forming the same.

A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 1×10.sup.2 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.

The present invention relates to a ruthenium thin film-forming method for forming a ruthenium thin film using a ruthenium precursor, in which tricarbonyl (η.sup.4-methylene-1,3-propanediyl) ruthenium ((CO).sub.3Ru-TMM)) having a structure represented by the following formula 1 is used as the ruthenium precursor, and the method includes a stage of forming a ruthenium thin film by an atomic layer deposition at a temperature ranging from 200° C. to 350° C. using this ruthenium precursor and a reaction gas. As the reaction gas, one or more selected from the group consisting of oxygen, hydrogen, water and ammonia are preferably applied.

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A component carrier includes a stack with an electrically conductive layer structure and an electrically insulating layer structure. The electrically conductive layer structure having a first plating structure and a pillar. The pillar has a seed layer portion on the first plating structure and a second plating structure on the seed layer portion. A method of manufacturing such a component carrier and an arrangement including such a component carrier are also disclosed.