A highly reliable memory device is provided. In a method for manufacturing a memory device that includes a first insulator, a first conductor including a first opening over the first insulator, a second insulator including a second opening over the first conductor, a second conductor including a third opening over the second insulator, a third insulator over the second conductor, and a semiconductor provided in the first opening to the third opening, the first insulator is formed, the first conductor is formed over the first insulator, the second insulator is formed over the first conductor, a fourth insulator is formed over the second insulator, the third insulator is formed over the fourth insulator, the third opening is formed in the fourth insulator, the second opening is formed in the second insulator, the first opening is formed in the first conductor, the semiconductor is formed in the first opening to the third opening, the fourth insulator is removed, and the second conductor is formed between the second insulator and the third insulator.

A novel semiconductor device is provided. A structure body extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction are provided. In a first intersection portion where the structure body and the first conductor intersect with each other, a first insulator, a first semiconductor, a second insulator, a second semiconductor, a third insulator, a fourth insulator, and a fifth insulator are provided concentrically around a third conductor. In a second intersection portion where the structure body and the second conductor intersect with each other, the first insulator, the first semiconductor, the second insulator, a fourth conductor, the second semiconductor, and the third insulator are provided concentrically around the third conductor.

A semiconductor device includes a substrate. A gate insulating film is formed on the surface of the substrate. A first gate electrode layer is formed on the gate insulating film. A second gate electrode layer is formed on the first gate electrode layer and electrically connected to the first gate electrode layer. A first contact extends through the second gate electrode layer to reach the first gate electrode layer. First and second impurity layers are formed on opposite sides of the first and second gate electrode layers.

An approach for utilizing an IC (integrated circuit) that is capable of storing multi-bit in storage is disclosed. The approach leverages the use of multiple nanowires structures as channels in a gate of a transistor. The use of multiple nanowires as channels allows for different V.sub.t (i.e., voltage of device) to be dependent on the thickness of the fe (ferroelectric layer) that surrounds each of the nanowire channels. Memory window is about 2d (thickness of a fe layer). Setting voltage is also proportional to the fe layer thickness. The V.sub.t of the device is the superposition of the various fe layers. For example, if there are three channels with three different Fe layer (of varying thickness), then four memory states can be achieved. More states can be achieved based on the number of channels in the device.

The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.

Memory cells having a first dielectric between a charge storage material and a semiconductor, conductive nanodots between the charge storage material and a control gate, and a second dielectric between the control gate and the conductive nanodots.

An organic light emitting display device includes a substrate, a buffer layer, an active layer, a gate insulation layer, a protective insulating layer, a gate electrode, an insulating interlayer, source and drain electrodes, and a sub-pixel structure. The buffer layer is disposed on the substrate. The active layer is disposed on the buffer layer, and has a source region, a drain region, and a channel region. The gate insulation layer is disposed in the channel region on the active layer. The protective insulating layer is disposed on the buffer layer, the source and drain regions of the active layer, and the gate insulation layer. The gate electrode is disposed in the channel region on the protective insulating layer. The insulating interlayer is disposed on the gate electrode. The source and drain electrodes are disposed on the insulating interlayer.

A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

A method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin; forming a first dielectric layer around the first dummy gate structure and around the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure to form a first recess and a second recess in the first dielectric layer, respectively; forming a gate dielectric layer in the first recess and the second recess; forming a first work function layer over the gate dielectric layer in the first and the second recesses; removing the first work function layer from the first recess; converting a surface layer of the first work function layer in the second recess into an oxide; and forming a second work function layer in the first recess over the gate dielectric layer and in the second recess over the oxide.

A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise opposing laterally-outer longitudinal edges. The longitudinal edges individually comprise a longitudinally-elongated recess extending laterally into the respective individual wordline. Methods are disclosed.