In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

A FinFET device structure and method for forming the same are provided. The method includes forming a fin structure over a substrate and forming a dummy gate electrode over a middle portion of the fin structure. The method also includes forming a spacer layer on the dummy gate electrode and on the fin structure and performing a plasma doping process on the dummy gate electrode and on the spacer layer. The method further includes performing an annealing process, wherein the annealing process is performed by using a gas comprising oxygen, such that a doped region is formed in a portion of the fin structure, and the spacer layer is doped with oxygen after the annealing process.

According to one embodiment, a semiconductor device includes first to sixth semiconductor regions, a first electrode, and a first insulating film. The first semiconductor region includes first and second partial regions. The second semiconductor region is separated from the first partial region in a second direction crossing a first direction. The third semiconductor region is provided between the first partial region and the second semiconductor region. The fourth semiconductor region is provided between the first partial region and the third semiconductor region. The first electrode is separated from the second partial region, the second and third semiconductor regions, and a portion of the fourth semiconductor region. The first insulating film contacts the third semiconductor region. The fifth semiconductor region is provided between the first insulating film and the second partial region. The sixth semiconductor region is provided between the first insulating film and the fifth semiconductor region.

According to one embodiment, a semiconductor device includes first to sixth semiconductor regions, a first electrode, and a first insulating film. The first semiconductor region includes first and second partial regions. The second semiconductor region is separated from the first partial region in a second direction crossing a first direction. The third semiconductor region is provided between the first partial region and the second semiconductor region. The fourth semiconductor region is provided between the first partial region and the third semiconductor region. The first electrode is separated from the second partial region, the second and third semiconductor regions, and a portion of the fourth semiconductor region. The first insulating film contacts the third semiconductor region. The fifth semiconductor region is provided between the first insulating film and the second partial region. The sixth semiconductor region is provided between the first insulating film and the fifth semiconductor region.

The present invention relates to a method for manufacturing a thin film transistor and an array substrate, and corresponding devices. In the thin film transistor manufacturing process, the base substrate is annealed after the formation of the patterns of the active layer, the source and the drain in the thin film transistor, so as to thermally diffuse ions of the source and the drain at an ohmic contact between the active layer and the source, as well as the drain, to the active layer, and further to provide the active layer with ions of the source and the drain for changing the components of the active layer, which reduces the resistance at the ohmic contact between the active layer and the source, as well as the drain, and guarantees the uniformity and reliability of the thin film transistor. Moreover, annealing treatment is relatively simpler in implementation as compared with the plasma treatment, and will not increase the complexity of the method for manufacturing the entire thin film transistor, which is good for thin film transistor production efficiency.

In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin.

A method for fabricating a semiconductor package, the method includes forming at least one conductive via having a first end and a second end opposite the first end in a wafer, in which the wafer has a first surface and a second surface opposite the first surface, and the first end of the at least one conductive via is exposed of the first surface of the wafer; grinding the second surface of the wafer to form an inner portion and a ring portion surrounding the inner portion of the wafer, wherein the inner portion has a thinner thickness than that of the ring portion; and etching the inner portion to expose the second end of the at least one conductive via.

The invention provides a sulfur doping method for graphene, which comprises the steps of: 1) providing graphene and placing the grapheme in a chemical vapor deposition reaction chamber; 2) employing an inert gas to perform ventilation and exhaust treatment in the reaction chamber; 3) introducing a sulfur source gas to perform sulfur doping on the graphene at 500-1050 C.; and 4) cooling the reaction chamber in a hydrogen and inert gas atmosphere. The present invention can perform sulfur doping on the graphene simply and efficiently, the economic cost is low, and large-scale production can be realized. Large area sulfur doping on graphene can be realized, and doping of graphene on an insulating substrate or metal substrate can be carried out directly.

The present invention relates to a method for manufacturing a transistor according selective printing of a dopant. For the manufacture of a transistor, a semiconductor layer is formed on a substrate, and a dopant layer is formed on the semiconductor layer. In the formation of the dopant layer, an inkjet printing is used to selectively print an n type dopant or a p type dopant.