An interconnect board includes: a first substrate; a second substrate having an outer shape smaller than an outer shape of the first substrate and mounted on the first substrate; and an adhesive layer bonding the first substrate and the second substrate together and having a fillet contacting a side surface of the second substrate. The fillet has a raised portion raised from a level of a top surface of the second substrate to a level higher than the top surface of the second substrate.

An electronic device package structure including a substrate, a first circuit layer, a second circuit layer, an electronic device and an input/output device is provided. The first circuit layer includes a first conductive portion, a second conductive portion and a first curve portion located between the first conductive portion and the second conductive portion. At least a partial thickness of the first curve portion is greater than a thickness of the first conductive portion. The electronic device disposed on the second circuit layer is electrically connected to the second conductive portion of the first circuit layer. The input/output device disposed corresponding to the first conductive portion is electrically connected to the first conductive portion of the first circuit layer.

A lead frame package including first conductive layer, first electronic component, lead frames, second conductive layer and package body. First conductive layer has conductive carriers. First electronic component has first pins. Lead frames and first pins are respectively electrically connected to conductive carriers. Second conductive layer has conductive joints respectively electrically connected to lead frames so as to be electrically connected to at least a part of conductive carriers via lead frames. Package body encapsulates first conductive layer, first electronic component, and lead frames. First conductive layer and second conductive layer are located on two opposite sides of first electronic component, respectively.

An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

A semiconductor structure including an integrated circuit die and conductive bumps is provided. The integrated circuit die includes bump pads. The conductive bumps are disposed on the bump pads. Each of the conductive bumps includes a first pillar portion disposed on one of the bump pads and a second pillar portion disposed on the first pillar portion. The second pillar portion is electrically connected to one of the bump pads through the first pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion. A package structure including the above-mentioned semiconductor structure is also provided.

A bonding system for bonding a semiconductor element to a substrate is provided. The bonding system includes a substrate oxide reduction chamber configured to receive a substrate. The substrate includes a plurality of first electrically conductive structures. The substrate oxide reduction chamber is configured to receive a reducing gas to contact each of the plurality of first electrically conductive structures. The bonding system also includes a substrate oxide prevention chamber for receiving the substrate after the reducing gas contacts the plurality of first electrically conductive structures. The substrate oxide prevention chamber has an inert environment when receiving the substrate. The bonding system also includes a reducing gas delivery system for providing a reducing gas environment during bonding of a semiconductor element to the substrate.

The invention relates to a method for producing an interconnection comprising a via (V) extending through a substrate (1), said method successively comprising: (a) the deposition of a layer (11) of titanium nitride or tantalum nitride on a main surface (1A) of the substrate and on the inner surface (10A, 10B) of at least one hole (10) extending into at least part of the thickness of said substrate; (b) the deposition of a layer (12) of copper on said layer (11) of titanium nitride or tantalum nitride; and (c) the filling of the hole (10) with copper, said method being characterized in that, during step (a), the substrate (1) is arranged in a first deposition chamber (100), and in that said step (a) comprises the injection of a titanium or tantalum precursor in a gaseous phase into the deposition chamber via a first injection path according to a first pulse sequence, and the injection of a nitrogen-containing reactive gas into the deposition chamber via a second injection path different from the first injection path according to a second pulse sequence, the first pulse sequence and the second pulse sequence being dephased.

A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b).

A MEMS device comprises an electro mechanical element in a sealed chamber containing a gas comprising a reactive gas selected to react with any contaminants that may be present or formed on the operating surfaces of the device in a manner to maximize the electrical conductivity of the surfaces during operation of the device. The MEMS device may comprise a MEMS switch having electrical contacts as the operating surfaces. The reactive gas may comprise hydrogen or an azane, optionally mixed with an inert gas, or any combination of the gases. The corresponding process provides a means to substantially reduce or eliminate contaminants present or formed on the operating surfaces of MEMS devices in a manner to maximize the electrical conductivity of the surfaces during operation of the devices.

A thin film transistor (TFT), a manufacturing method thereof, an array substrate and a display panel are disclosed. The manufacturing method includes: providing a base substrate; forming a first electrode, an isolating layer, an active layer and a gate insulating layer on the base substrate; simultaneously forming a second electrode and a gate electrode, wherein the second electrode is connected to the active layer.