A semiconductor chip package is provided with improved connections between different components within the package. The semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.

A component carrier includes a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure, a component embedded in the stack, and a via formed in the at least one electrically insulating layer structure along a horizontal path having a length being larger than a horizontal width.

A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.

A process of preparing a conductive oxide interface is described herein, comprising contacting a surface of a first oxide with a plasma of a reducing gas to obtain a treated surface, and depositing a second oxide on the treated surface, thereby obtaining a conductive oxide interface between the first oxide and the second oxide. Further described herein are composites and articles of manufacture comprising same, the composites comprising a first oxide and second oxide, and an interface between the first oxide and second oxide which comprises a conductive oxide interface, wherein the conductive oxide interface comprises nitrogen atoms and/or the second oxide is in an amorphous form and the conductive oxide interface is characterized by a sheet resistance of no more than 10.sup.5 omega/square.

Provided is a method for growing carbon nanotubes that enables the growth of high-density carbon nanotubes. A high frequency bias voltage is applied to a loading table on which a wafer W having a catalytic metal layer is mounted to generate a bias potential on the surface of the wafer W, and oxygen plasma is used to micronize the catalytic metal layer to form catalytic metal particles. Thereafter, hydrogen plasma is used to reduce the surface of the catalytic metal particles to form activated catalytic metal particles having an activated surface. By using each activated catalytic metal particles as a nucleus, carbon nanotubes are formed.

Provided is a semiconductor device having a top-gate structure resistant to creation of parasitic capacitance between a low-resistance region formed in a semiconductor layer and a gate electrode, and also provided region method for manufacturing the same and a display device including the same.

A TFT (100) has a low-resistance region, a portion of which has a first length (L1) ranging from a first position (P1) corresponding to an end of a gate insulating film to a region below a gate electrode (40), and the first length is substantially equal to a second length (L2) ranging from the first position (P1) to a second position (P2) corresponding to an end of the gate electrode (40). Thus, the overlap between the gate electrode (40) and either a source region (20s) or a drain region (20d) can be reduced, resulting in diminished parasitic capacitance.

Provided is a semiconductor device having a top-gate structure resistant to creation of parasitic capacitance between a low-resistance region formed in a semiconductor layer and a gate electrode, and also provided region method for manufacturing the same and a display device including the same.

A TFT (100) has a low-resistance region, a portion of which has a first length (L1) ranging from a first position (P1) corresponding to an end of a gate insulating film to a region below a gate electrode (40), and the first length is substantially equal to a second length (L2) ranging from the first position (P1) to a second position (P2) corresponding to an end of the gate electrode (40). Thus, the overlap between the gate electrode (40) and either a source region (20s) or a drain region (20d) can be reduced, resulting in diminished parasitic capacitance.

A vacuum package includes a substrate, a pair of through electrodes that penetrates the substrate, each of the pair of the trough electrodes having first end portion, and a getter that is joined to the first end portions of the pair of the through electrodes, and is heated by electronic conduction via the pair of the through electrodes A portion of the getter between the through electrodes is spaced apart from the substrate.

A vacuum package includes a substrate, a pair of through electrodes that penetrates the substrate, each of the pair of the trough electrodes having first end portion, and a getter that is joined to the first end portions of the pair of the through electrodes, and is heated by electronic conduction via the pair of the through electrodes A portion of the getter between the through electrodes is spaced apart from the substrate.

An interconnection technology may use molded solder to define solder balls. A mask layer may be patterned to form cavities and solder paste deposited in the cavities. Upon heating, solder balls are formed. The cavity is defined by spaced walls to keep the solder ball from bridging during a bonding process. In some embodiments, the solder bumps connected to the solder balls may have facing surfaces which are larger than the facing surfaces of the solder ball.