Methods of forming fine patterns having a width and a pitch in semiconductor devices may be used to form a semiconductor device or electronic device. The fine patterns may be formed by forming sacrificial pillars, which in certain examples may be formed from spacer patterns.

A method of forming a power rail to semiconductor devices that includes forming a gate structure extending from a first active region to a second active region of a substrate, and removing a portion of the gate structure forming a gate cut trench separating the first active region from the second active region. A fill material of an alternating sequence of at least two different composition conformally deposited dielectric layers is formed within the gate cut trench. A power rail is formed in the gate cut trench. An aspect ratio of the vertically orientated portions of the alternating sequence of the at least two different composition conformally deposited dielectric layer obstructs lateral etching of the gate cut trench during etching to form a power rail opening for housing the power rail.

A semiconductor device includes a semiconductor wafer including a plurality of first semiconductor die. An opening is formed partially through the semiconductor wafer. A plurality of second semiconductor die is disposed over a first surface of the semiconductor wafer. An encapsulant is disposed over the semiconductor wafer and into the opening leaving a second surface of the semiconductor wafer exposed. A portion of the second surface of the semiconductor wafer is removed to separate the first semiconductor die. An interconnect structure is formed over the second semiconductor die and encapsulant. A thermal interface material is deposited over the second surface of the first semiconductor die. A heat spreader is disposed over the thermal interface material. An insulating layer is formed over the first surface of the semiconductor wafer. A vertical interconnect structure is formed around the first semiconductor die. Conductive vias are formed through the first semiconductor die.

A memory device includes a semiconductor substrate, a peripheral circuit formed on a top surface of the semiconductor substrate, a lower insulation layer covering the peripheral circuit, a base layer formed on the lower insulation layer, a memory cell array formed on the base layer, an upper insulation layer covering the memory cell array and a plurality of input-output pads formed on a bottom surface of the semiconductor substrate. At least one of the input-output pads is disposed to be overlapped with a portion of the memory cell array in a vertical direction. The sizes of the memory device and the memory package including the memory device may be reduced through the COP structure and efficient arrangement of the input-output pads.

A method includes, for example, providing an intermediate semiconductor structure comprising a metallic layer, a patternable layer disposed over the metallic layer, and a hard mask disposed over the patternable layer, the intermediate semiconductor structure comprising a plurality of vias extending through the hard mask onto the metallic layer, depositing a sacrificial barrier layer over the intermediate semiconductor structure and in the plurality of vias, removing a portion of the sacrificial barrier layer between the plurality of vias while maintaining a portion of the sacrificial barrier layer in the plurality of vias, forming a trench in the patternable layer between the removed portion of the sacrificial barrier layer and the plurality of vias, and removing the remaining portions of the sacrificial barrier layer from the plurality of vias.

A multilayer circuit (400) includes a base layer (205) which has a number of base vias (247, 415), a first overlying layer (215) formed on the base layer (205) and having a first routing section (210) and a second overlying layer (220) formed on the first overlying layer (215). The second overlying layer (220) has a second routing section (210) and is formed using the same set of masks. The first routing section (210) and the second routing section (210) form a unique electrical pathway (248) between a base via (247) and an element in an overlying layer. A method for forming a multilayer circuit is also provided.

A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.

A standoff structure for providing improved interconnects is provided, wherein the structure employs nickel copper alloy or copper structures having increased resistivity.

A thin film transistor and a producing method thereof, and an array substrate, which belong to a technical field of the thin film transistor, can solve a problem of poor performance of a conventional thin film transistor. The producing method of the thin film transistor comprises: S1: forming a gate electrode (11) composed of graphene; S2: forming a gate insulating layer (12) composed of oxidized graphene; S3: forming an active region (13) composed of doped oxidized graphene or doped graphene; S4: forming a source electrode (14) and a drain electrode (15) composed of graphene, wherein, the graphene composing the source electrode (14), the drain electrode (15) and the gate electrode (11) is formed by reducing oxidized graphene, and the doped oxidized graphene or doped graphene composing the active region (13) is formed by treating oxidized graphene.

Provided is a fastening member which is a columnar fastening member, and the fastening member includes: a first hole provided in a direction parallel to a height direction of the fastening member; a thread on a side surface of the first hole; a planar portion around the first hole; and a projection between the planar portion and the first hole.