Patent classifications
H01L21/46
Direct and pre-patterned synthesis of two-dimensional heterostructures
A method for growing a transition metal dichalcogenide on a substrate, the method including providing a growth substrate having a first side and a second side opposite the first side; providing a source substrate having a first side and a second side opposite the first side; depositing a transition metal oxide on at least a portion of the first side of the source substrate; combining the growth substrate with the source substrate such that the first side of the growth substrate contacts the transition metal oxide, the combining producing a substrate stack; exposing the substrate stack to a chalcogenide gas, whereby the transition metal oxide reacts with the chalcogenide gas to produce a layer of a transition metal dichalcogenide on at least a portion of the first side of the growth substrate; and removing the source substrate from the growth substrate having the layer of the transition metal dichalcogenide thereon.
Printable inorganic semiconductor structures
The present invention provides structures and methods that enable the construction of micro-LED chiplets formed on a sapphire substrate that can be micro-transfer printed. Such printed structures enable low-cost, high-performance arrays of electrically connected micro-LEDs useful, for example, in display systems. Furthermore, in an embodiment, the electrical contacts for printed LEDs are electrically interconnected in a single set of process steps. In certain embodiments, formation of the printable micro devices begins while the semiconductor structure remains on a substrate. After partially forming the printable micro devices, a handle substrate is attached to the system opposite the substrate such that the system is secured to the handle substrate. The substrate may then be removed and formation of the semiconductor structures is completed. Upon completion, the printable micro devices may be micro transfer printed to a destination substrate.
Device boost by quasi-FinFET
Some embodiments relate to an integrated circuit (IC) including one or more field-effect transistor devices. A field effect transistor device includes source/drain regions disposed in an active region of a semiconductor substrate and separated from one another along a first direction by a channel region. A shallow trench isolation (STI) region, which has an upper STI surface, laterally surrounds the active region. The STI region includes trench regions, which have lower trench surfaces below the upper STI surface and which extend from opposite sides of the channel region in a second direction which intersects the first direction. A metal gate electrode extends in the second direction and has lower portions which are disposed in the trench regions and which are separated from one another by the channel region. The metal gate electrode has an upper portion bridging over the channel region to couple the lower portions to one another.
MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
A semiconductor device including an oxide conductor with high conductivity and high transmittance is provided. A manufacturing method for a semiconductor device includes the steps of: forming an oxide semiconductor over a first insulator; forming a second insulator over the first insulator and the oxide semiconductor; forming a first conductor over the second insulator; forming an etching mask over the first conductor; forming a second conductor including a region overlapping with the oxide semiconductor by etching the first conductor with use of the etching mask as a mask; removing the etching mask; and performing heat treatment after forming a hydrogen-containing layer over the second insulator and the second conductor.
Composite substrate manufacturing method, and composite substrate
Disclosed is a composite substrate manufacturing method whereby, after bonding a semiconductor substrate (1) and a supporting substrate (3) to each other, the semiconductor substrate (1) is thinned, and a composite substrate (8) having a semiconductor layer (6) on the supporting substrate (3) is obtained. On the supporting substrate (3) surface to be bonded, a coating film (4a) containing polysilazane is formed, a silicon-containing insulating film (4) is formed by performing firing by heating the coating film (4a) to 600-1,200 C., then, the semiconductor substrate (1) and the supporting substrate (3) are bonded to each other with the insulating film (4) therebetween, thereby suppressing bonding failures due to surface roughness and defects of the supporting substrate, and easily obtaining the composite substrate.
Method of marking a semiconductor package
A method of making a semiconductor device can include providing a wafer comprising a plurality of semiconductor die, wherein each semiconductor die comprises an active surface and a backside opposite the active surface. A photosensitive layer can be formed over the wafer and on a backside of each of the plurality of semiconductor die within the wafer with a coating machine. An identifying mark can be formed within the photosensitive layer for each of the plurality of semiconductor die with a digital exposure machine and a developer, wherein a thickness of the identifying mark is less than or equal to 50 percent of a thickness of the photosensitive layer. The photosensitive layer can be cured. The wafer can be singulated into a plurality of semiconductor devices.
UV-cure pre-treatment of carrier film for wafer dicing using hybrid laser scribing and plasma etch approach
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side of the semiconductor wafer includes adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier. Subsequent to adhering the semiconductor wafer on a dicing tape, the dicing tape is treated with a UV-cure process. Subsequent to treating the dicing tape with the UV-cure process, a dicing mask is formed on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits. The dicing mask is patterned with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the dicing mask layer to singulate the integrated circuits.
Methods of processing substrates
Methods processing substrates are provided. The method may include providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting glue layer and thermosetting release layers provided on opposing sides of the thermosetting glue layer.
Thin film structure including metal seed layer and method of forming oxide thin film on transparent conductive substrate by using the metal seed layer
A thin film structure includes a metal seed layer, and a method of forming an oxide thin film on a conductive substrate by using the metal seed layer is disclosed. The thin film structure includes a transparent conductive substrate, a metal seed layer that is deposited on the transparent conductive substrate, and a metal oxide layer that is deposited on the metal seed layer.
ARCHITECTURES AND METHODS TO MODULATE CONTACT RESISTANCE IN 2D MATERIALS FOR USE IN FIELD EFFECT TRANSISTOR DEVICES
Hybrid bonding interconnect (HBI) architectures for scalability. Embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. The conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. Some embodiments implement a non-bonding moisture seal ring (MSR) structure.