The invention relates to a method for producing optoelectronic components. The invention comprises: provision of a metal substrate, the substrate having a front side and a rear side opposite the front side; front-side removal of substrate material such that the substrate comprises substrate sections protruding in the region of the front side and recesses arranged there between; formation of a plastic body adjacent to substrate sections; arrangement of optoelectronic semiconductor chips on substrate sections; rear-side removal of substrate material in the region of the recesses, such that the substrate is structured into separate substrate sections; and performance of a separation process. The plastic body is divided into separate substrate sections and individual optoelectronic components with at least one optoelectronic semiconductor chip are formed. The invention also relates to an optoelectronic component.

Implementations of semiconductor packages may include: a die coupled to a glass lid; one or more inner walls having a first material coupled to the die; an outer wall having a second material coupled to the die; and a glass lid coupled to the die at the one or more inner walls and at the outer wall; wherein the outer wall may be located at the edge of the die and the glass lid and the one or more inner walls may be located within the perimeter of the outer wall at a predetermined distance from the perimeter of the outer wall; and wherein a modulus of the first material may be lower than a modulus of the second material.

A foil-based package and a method for manufacturing a foil-based package includes, among other things, a first and a second foil substrate. An electronic component is arranged between the two foil substrates in a sandwich-like manner. Due to the component thickness, there is a distance difference between the two foil substrates between the mounting area of the component and ears outside of the mounting area. The foil-based package and the method provides means for reducing and/or compensating a distance difference between the first foil substrate and the second foil substrate caused by the component thickness.

Direct growth methods for preparing diamond-assisted heat-dissipation silicon carbide substrates of GaN-HEMTs are disclosed. In an embodiment, the direct growth method includes the following steps: (1) etching holes in a surface of a silicon carbide substrate to produce a silicon carbide wafer; (2) ultrasonic cleaning the produced silicon carbide wafer; (3) establishing an auxiliary nucleation point on a surface of the silicon carbide wafer; (4) depositing a diamond layer; (5) removing the portion of the diamond layer on the upper surface while retaining the portion of the diamond layer in the holes; (6) ultrasonic cleaning; and (7) depositing diamond in the holes on the silicon carbide wafer until the holes are fully filled.

A semiconductor device includes an insulating carrier structure comprised of an insulating inorganic material. The carrier structure has a receptacle in which a semiconductor chip is disposed. The semiconductor chip has a first side, a second side and a lateral rim. The carrier structure laterally surrounds the semiconductor chip and the lateral rim. The semiconductor device also includes a metal structure on and in contact with the second side of the semiconductor chip and embedded in the carrier structure.

Techniques of minimizing or eliminating stresses in silicon photonic integrated circuits (Si-PICs) and in semiconductor packages having one or more Si-PICs (Si-PIC packages) are described. An Si-PIC or an Si-PIC package includes a stress minimization solution that assists with filtering out stresses by selectively isolating photonic and/or electronic devices, by isolating components or devices in an Si-PIC or an Si-PIC package that are sources of stress, or by isolating an Si-PIC in an Si-PIC package. The stress minimization solution may include strategically placed cavities and a stage that assist with minimizing or preventing transfer of stress to one or more photonic and/or electronic devices in an Si-PIC or an Si-PIC package.

An electronic circuit board includes: electronic components; a silicon board that is plate shaped, includes a wiring pattern provided on at least one of a surface and a reverse surface thereof, and includes recessed portions where the electronic components are individually mounted; and a supporting board that is layered over the reverse surface of the silicon board, and includes a wiring pattern provided on at least one of a surface and a reverse surface thereof. Side faces of the recessed portions are perpendicular to the surface of the silicon board, the wiring pattern is connected to at least one of the electronic components mounted in the recessed portions, via at least one of a via and a bottom surface electrode provided in of the at least one of the recessed portions, and the recessed portions penetrate through the silicon board.

A semiconductor structure with a back gate includes a device wafer includes a front side and a back side. A transistor is disposed on the front side, wherein the transistor includes a gate structure, a source and a drain. An interlayer dielectric covers the transistor. A first metal layer and a second metal layer are within the interlayer dielectric. A first conductive plug is within the interlayer dielectric and contacts the source and the first metal layer. A second conductive plug is disposed within the interlayer dielectric and contacts the drain and the second metal layer. A back gate, a source conductive pad and a drain conductive pad are disposed on the back side. A first via plug penetrates the device wafer to electrically connect the source conductive pad and the source. A second via plug penetrates the device wafer to electrically connect the drain conductive pad and the drain.

The present invention relates to an electronic unit having at least one first electronic component and one second electronic component that are fastened to a substrate. A shielding is arranged between the first and second electronic components that comprises an elevated portion that projects from a plane defined by the substrate or that extends from its surface, that acts as a shielding and that is formed in one piece with the substrate.

A component carrier having a base structure consisting of an electrically conductive material, an electronic component arranged on the base structure and a surrounding structure on the base structure, where the surrounding structure at least partially surrounds the electronic component laterally.