A semiconductor device has a semiconductor package including a substrate with a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A metal mask having a fiducial marker is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The metal mask is removed after forming the shielding layer.

Methods for protecting edges of semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, a plurality of trenches may be formed on a front side of a substrate including a plurality of semiconductor dies. Individual trenches may correspond to scribe lines of the substrate where each trench includes a depth greater than a final thickness of the semiconductor dies. A dielectric layer may be formed on sidewalls of the trenches, thereby protecting the edges of the semiconductor dies, prior to filling the trenches with an adhesive material. Subsequently, the substrate may be thinned from a back side such that the adhesive material in the trenches may be exposed from the back side. The adhesive material may be removed to singulate individual semiconductor dies of the plurality from the substrate.

A method for manufacturing a semiconductor structures is provided. The method includes forming a first hybrid bonding layer over a first wafer having a logic structure, forming a second hybrid bonding layer over a second wafer having a first capacitor structure, bonding the first wafer and the second wafer through a hybrid bonding operation to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer, and the first capacitor structure is electrically connected to the logic structure through the first hybrid bonding layer and the second hybrid bonding layer, and singulating the first bonded wafer to obtain a plurality of semiconductor structures.

Disclosed are a conductive particle, an anisotropic conductive film, a display device, and a method for fabricating the same so as to detect the extent to which the conductive particles are cracked in a heating and pressurizing process, to thereby improve the ratio of finished products while the display device is being manufactured. A core of the conductive particle is a fluorescent resin core. In the conductive particle according to this disclosure, the core of the conductive particle is a fluorescent resin core, and the extent to which the conductive particle is cracked can be detected by detecting varying fluorescence in a heating and pressuring process, to thereby alleviate such a phenomenon from taking place that the conductive particle has a poor electrical conductivity due to an insufficient pressure, or the conductive particle is cracked, and thus loses its electrical conductivity, due to an excessive pressure.

Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

A system for semiconductor wafer testing, a tangent probe card and a probe head assembly thereof. The system has a tangent probe card and a tester. Testing ends of the probe card are flat, hence the allowable alignment budget will always be more generous for the tangent probe card. The probes are held on the probe head assembly, and once the alignment is achieved accurately during manufacture, the alignment will remain stable throughout the whole life cycle. The probe has a greater CCC due to its larger cross section. The throughput of the tangent probes is higher than that of the conventional probe card since there is no need to move the pointed pin/structure. No pointed pin/structure needs to be repaired, and the flat bottom surface of the probe head assembly is easier to clean and maintain.

An apparatus includes a first substrate including one or more electrical connection features; and an assembly including: a second substrate; conductive features formed on the second substrate, one or more of which are electrically connected to corresponding electrical connection features of the first substrate; and an electronic component between the second substrate and the first substrate and electrically connected to one or more of the conductive features.

In a general aspect, a for producing a fan-out wafer level package (FOWLP) semiconductor device can include separating a semiconductor wafer into a plurality of semiconductor die and, after separating the semiconductor wafer into the plurality of semiconductor die, increasing spacing between the plurality of semiconductor die. The method can further include encapsulating, in a molding compound, the plurality of semiconductor die and determining respective locations of one or more alignment features disposed within the molding compound. The method can still further include forming, based on the determined respective locations, one or more alignment marks in the molding compound.

A high-frequency device manufacturing method is provided. The method includes providing a substrate; forming a conductive material on the substrate; standing the substrate and the conductive material for a first time duration; forming a conductive layer by sequentially repeating the steps of forming the conductive material and standing at least once; and patterning the conductive layer. The thickness of the conductive layer is in a range from 0.9 m to 10 m. A high-frequency device is also provided.

To provide a sheet for sintering bonding and the same with a base material suited for lamination and integration and also suited for realizing satisfactory operational efficiency in a sintering process in a process of producing semiconductor devices that go through sintering bonding of semiconductor chips. A sheet for sintering bonding 10 of the present invention comprises an electrically conductive metal containing sinterable particle and a binder component. In this sheet, the minimum load, reached during an unloading process in load-displacement measurement according to a nanoindentation method, is 100 to 30 N. Alternatively, the ratio of the minimum load to a maximum load, reached during a load applying process in the above measurement, is 0.2 to 0.06. A sheet body X, a sheet for sintering bonding with a base material of the present invention, has a laminated structure comprising a base material B and the sheet 10.