Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.

A method of manufacturing a semiconductor device is provided, which includes the steps of providing a capacitor structure, forming a conductive layer on the capacitor structure, performing a hydrogen doping process to the conductive layer, forming a metal layer on the conductive layer after the hydrogen doping process, and patterning the metal layer and the conductive layer to forma top electrode plate.

This invention can be used as mini-micro-switching, up to macro switching. An electronic module having several input copper circuit traces, and several output copper traces, or wires, with some traces having disconnects, consisting of drilled holes, which can be bridged by conductive fasteners. This invention is also solving switching of differing functions both in the industry, and after that the product is in the market and the customer requests switching options. Selecting a switching options can be accomplished on a module, by first remove a conductive fastener from one position and attach the fastener in a second position on copper traces. Where the fastener is removed and not re-inserted, an open circuit trace occurs. Thereby accomplishing: selecting, reversing, or switching of one, or of a multiple of circuits.

A semiconductor package device includes a substrate, an electronic component, a bonding wire, a heat spreader, a thermal conductive structure and an encapsulant. The electronic component is disposed on the substrate. The bonding wire connects the electronic component to the substrate. The heat spreader is disposed over the electronic component. The thermal conductive structure is disposed between the heat spreader and the electronic component. The thermal conductive structure includes two polymeric layers and a thermal conductive layer. The conductive layer is disposed between the two polymeric layers. The thermal conductive layer has a first end in contact with the electronic component and a second end in contact with the heat spreader. The encapsulant covers the bonding wire.

A technique for marking semiconductor devices with an identifiable mark or alphanumeric text yields a high-contrast, easily distinguishable mark on an electrical terminal of the device without impacting the device's breakdown voltage capability and without compromising the solderability and wire bondability of the terminal. This approach deposits the mark on the terminal as a patterned layer of palladium, which offers good contrast with the base metal of the terminal and maintains the solderability and bondability of the terminal.

A semiconductor device includes: a frame; a first-external-terminal provided to a first side portion of the frame; a first substrate enclosed in the frame and having a first-conductive-layer at an upper surface; a first-semiconductor-element: mounted on the first-conductive-layer; having, on a lower surface, a first main electrode connecting with the first-conductive-layer; and having a second main electrode and a control electrode on an upper surface; a first terminal connecting portion establishing a connection between the first-external-terminal and an exposed portion of the first-conductive-layer between the first-semiconductor-element and the first-external-terminal; a first-external-control-terminal provided above a wire in the frame and between the first main electrode of the first-semiconductor-element and the first-external-terminal; and a first control terminal connecting portion establishing a connection: between the control electrode of the first-semiconductor-element and the first-external-control-terminal; and above a wire between the first main electrode of the first-semiconductor-element and the first-external-terminal.

A package structure includes a spiral coil, a redistribution layer (RDL) and a molding material. The molding material fills gaps of the spiral coil. The spiral coil is connected to the RDL. A fan-out package structure includes a spiral coil, an RDL and a die. The spiral coil has a depth-to-width ratio greater than about 2. The RDL is connected to the spiral coil. The die is coupled to the spiral coil through the RDL. A semiconductor packaging method includes: providing a carrier; adhering a spiral coil on the carrier; adhering a die on the carrier; dispensing a molding material on the carrier to fill gaps between the spiral coil and the die; and disposing a redistribution layer (RDL) over the carrier so as to connect the spiral coil with the die.

A semiconductor package device comprises a first dielectric layer, a first conductive pad and a first conductive element. The first dielectric layer has a first surface and a second surface opposite to the first surface. The first dielectric layer defines a first opening tapered from the first surface toward the second surface. The first conductive pad is within the first opening and adjacent to the second surface of the first dielectric layer. At least a portion of the first conductive element is within the first opening. The first conductive element is engaged with (e.g., abuts) a sidewall of the first opening, the first conductive element having a first surface facing toward the first conductive pad, wherein the first surface of the first conductive element is spaced apart from the first conductive pad.

A metal heat slug having an upper and lower surface is provided. First and second electrically conductive leads are provided. First and second electrically insulating fastening mechanisms are provided. The first and second fastening mechanisms are adhered to the upper surface of the heat slug in an outer peripheral region of the heat slug such that the first and second leads are vertically separated from and electrically insulated from the heat slug. The central die attach region is exposed from the first and second fastening mechanisms after adhering the first and second fastening mechanisms to the upper surface of the heat slug.

An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18?10.sup.?6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.