Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.

A semiconductor structure is provided. The semiconductor structure includes a substrate; and a plurality of parallel first conductive layers formed on the substrate. The semiconductor structure also includes a composite magnetic structure having a plurality of magnetic layers and a plurality of insulation layers with a sandwich arrangement formed on a portion of the substrate and portions of surfaces of the plurality of first conductive layers. Further, the semiconductor structure includes a plurality of first conductive vias and a plurality of second conductive vias formed on the first conductive layers at both sides of the composite magnetic structure. Further, the semiconductor structure also includes a plurality of second conductive layers formed on a top surface of the composite magnetic structure, top surfaces of the first conductive vias, and top surfaces of the second conductive vias to form at least one coil structure wrapping around the composite magnetic structure.

The methods of the present disclosure enable formation of highly conductive contacts that facilitate in increasing the device speed and lowering the operating voltages of semiconductor devices such as, but not limited to, metal-on-semiconductor (MOS) transistors and the like. In one embodiment, the methods create the optimal contacts, useful in N type or P type MOS devices, by forming metal-insulator-semiconductor (MIS) contact structure or a non-stoichiometric layer contact structure. It is noted that N type or P type contacts require different work function metals to achieve a low Schottky barrier height (SBH).

A method of forming an integrated circuit, including providing a first substrate layer having a center piece and two side pieces on opposite sides of the center piece, assembling one or more circuit elements on a top side and a bottom side of the center piece of the first substrate layer, preparing two support pieces from a substrate, matching the size of the side pieces, coupling the support pieces to the bottom of the first substrate layer under the side pieces to form a second substrate layer with a void in the center under the center piece of the first substrate layer; and wherein the side pieces and support pieces include via connectors electrically connecting between a bottom side of the second substrate layer and the circuit elements.

An apparatus is provided, comprising a substrate with a frontside and a backside opposite the frontside; control circuitry disposed over the frontside of the substrate; a memory array disposed over and electrically coupled to the control circuitry; a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the backside of the substrate; and a bond pad disposed on the backside of the substrate and electrically coupled to the control circuitry via the TSV.

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor substrate; a first dielectric layer; a second dielectric layer; a waveguide; a heater; a first conductive layer; a conductive contact; and a second conductive layer. The first dielectric layer is disposed on the semiconductor substrate. The second dielectric layer is disposed on the first dielectric layer. The waveguide is disposed in the first dielectric layer. The heater is disposed in the second dielectric layer and above the waveguide. The first conductive layer comprises a plurality of first conductive interconnects disposed above the heater. The conductive contact is electrically connected to the heater and disposed between the heater and the first conductive layer. The second conductive layer comprises a plurality of second dummy interconnects.

An apparatus is provided, comprising a substrate with a frontside and a backside opposite the frontside; control circuitry disposed over the frontside of the substrate; a memory array disposed over and electrically coupled to the control circuitry; a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the backside of the substrate; and a bond pad disposed on the backside of the substrate and electrically coupled to the control circuitry via the TSV.

Disclosed herein is a method for producing a land grid array (LGA) socket connector assembly and the resultant assembly. The method comprises providing a carrier having a first carrier thickness with an array of vias, each having a first diameter, providing pockets around top surfaces of the vias, each having a second diameter and creating a portion of the pockets having a second carrier thickness that is less than the first carrier thickness, providing socket contact springs, each comprising a hole support structure that supports the socket contact spring within the via, and a contact beam configured to contact a conductor of an integrated circuit to be placed within the socket connector assembly, wherein a portion of carrier having a first carrier thickness is configured to prevent the contact beam from inelastically deforming when bent under load. Alternately, a contact feature may be used to prevent the inelastic deformation.

A semiconductor device is formed using a jig. The jig includes a metal frame, a polymer film, and an adhesive layer disposed between the metal frame and polymer film. An opening is formed through the adhesive layer and polymer film. A groove is formed around the opening. A semiconductor package is disposed on the jig over the opening with a side surface of the semiconductor package adjacent to the groove. A shielding layer is formed over the semiconductor package and jig. The semiconductor package is removed from the jig.

A semiconductor apparatus includes: (i) a semiconductor device; (ii) a first external connection terminal configured to be connected to the semiconductor device, and includes a first surface; and a second surface; and (iii) an insulating resin enclosure. The first external connection terminal includes: a base part that is embedded in the insulating resin enclosure; and a protruding part that protrudes from the inner wall of the insulating resin enclosure. The second surface includes: a first part that corresponds to the protruding part; and a second part that corresponds to the base part and is exposed by the first recessed part. The first part and the second part are continuous with each other along a second direction. The first and second extending parts are spaced apart from each other in a third direction. Each of the first and second extending parts extends along the first direction from a position corresponding to the second surface of the first external connection terminal.