Various embodiments described herein provide analog sense points for circuit die, which can form part of an integrated circuit (IC) package and can facilitate measurement of at least a portion of the circuit die using a Kelvin method of measurement.

Various embodiments described herein provide analog sense points for circuit die, which can form part of an integrated circuit (IC) package and can facilitate measurement of at least a portion of the circuit die using a Kelvin method of measurement.

A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.

A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.

A bonded structure comprises a frame element having a cavity formed through its thickness. The frame element is directly bonded to a first element at a first side and to a second element at a second side enclosing the cavity. The frame element may comprise a through substrate via (TSV). Redundant conductive contact pads may be formed in bonding layers for enhanced direct bonding quality and reliability.

A bonded structure comprises a frame element having a cavity formed through its thickness. The frame element is directly bonded to a first element at a first side and to a second element at a second side enclosing the cavity. The frame element may comprise a through substrate via (TSV). Redundant conductive contact pads may be formed in bonding layers for enhanced direct bonding quality and reliability.

A method of manufacturing a semiconductor device, including preparing a heat-dissipating base, performing a first initial warping or a second initial warping of the heat-dissipating base, soldering a laminated substrate, including a circuit board provided on an insulating board, on the heat-dissipating base after the first or second initial warping, and soldering a semiconductor chip on the circuit board. The first initial warping includes performing shot peening on the rear surface of the heat-dissipating base to form a hardened layer, and subsequently plating the front and rear surfaces of the heat-dissipating base, including the hardened layer formed thereon, with a metal material. The second initial warping includes plating the front and rear surfaces of the heat-dissipating base with the metal material to form a plating layer, and subsequently performing the shot peening on the rear surface of the heat-dissipating base, including the plating layer formed thereon, with the metal material.

A carrier substrate having a plurality of receptacles each for receiving and carrying a semiconductor chip is provided. Semiconductor chips are arranged in the receptacles, and metal is plated in the receptacles to form a metal structure on and in contact with the semiconductor chips. The carrier substrate is cut to form separate semiconductor devices.

A carrier substrate having a plurality of receptacles each for receiving and carrying a semiconductor chip is provided. Semiconductor chips are arranged in the receptacles, and metal is plated in the receptacles to form a metal structure on and in contact with the semiconductor chips. The carrier substrate is cut to form separate semiconductor devices.

A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.