A method for producing singulated encapsulated components. The method includes the steps of application of a frame structure on a substrate surface of a substrate, wherein the frame structure surrounds components arranged on the substrate surface; bonding of a cover substrate on the frame structure; hardening of the frame structure; and singulation of the encapsulated components, wherein the frame structure is formed from an adhesive.

A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.

A low temperature rapid curing type low elastic conductive adhesive is provided which is useful as a conductive adhesive for component mounting in a field of FHE. The conductive resin composition contains (A) at least two types of urethane acrylate oligomers, (B) a radical polymerizable monomer, (C) a free radical generation curing agent, and (D) conductive particle. In the conductive resin composition, the component (A) preferably contains a high molecular weight urethane acrylate oligomer having a weight average molecular weight of 10,000 or more (A1), and a low molecular weight urethane acrylate oligomer having a weight average molecular weight of 9,999 or less (A2).

The present invention provides a mounting apparatus and a parallelism detection method in the mounting apparatus. The parallelism detection method in the mounting apparatus includes: a first height detection process of detecting first heights of a mounting tool when a holding surface comes into contact with the a tip of a triangular pin by placing the triangular pin on a placement surface of a stage and lowering the mounting tool; a second height detection process of detecting second heights of the mounting tool when the tip of the triangular pin comes into contact with the placement surface by holding the triangular pin on the holding surface of the mounting tool and lowering the mounting tool; and a parallelism calculation process of calculating the parallelism between the placement surface of the stage and the holding surface of the mounting tool based on the first heights and the second heights.

In one example, an electronic device comprises a cavity substrate comprising a substrate base comprising a top side and a bottom side and a cavity wall over the substrate base and defining a cavity, an electronic component over the substrate base and in the cavity, a lid comprising a top side and a bottom side, wherein the lid is over the substrate base and the cavity wall to define an interior of the cavity and an exterior of the cavity, an adhesive between the bottom side of the lid and a top side of the cavity wall, and a vent seal between the interior of the cavity and the exterior of the cavity. Other examples and related methods are also disclosed herein.

In one example, an electronic device comprises a cavity substrate comprising a substrate base comprising a top side and a bottom side and a cavity wall over the substrate base and defining a cavity, an electronic component over the substrate base and in the cavity, a lid comprising a top side and a bottom side, wherein the lid is over the substrate base and the cavity wall to define an interior of the cavity and an exterior of the cavity, an adhesive between the bottom side of the lid and a top side of the cavity wall, and a vent seal between the interior of the cavity and the exterior of the cavity. Other examples and related methods are also disclosed herein.

The present invention includes: a position detection unit (55) detecting positions of semiconductor chips and storing each detected position in a position database (56); a position correction unit (57) outputting a corrected bonding position; and a bonding control unit (58) performing bonding of the semiconductor chips based on the corrected bonding position input from the position correction unit (57). The position correction unit (57) calculates position shift amounts between the semiconductor chips of respective stages and an accumulated position shift amount, and when the accumulated position shift amount is greater than or equal to a predetermined threshold value, corrects the position of the semiconductor chip by the accumulated position shift amount and outputs it as the corrected bonding position, and the bonding control unit (58) performs bonding of the semiconductor chip of the next stage at the corrected bonding position input from the position correction unit.

A package assembly includes an interposer module on a package substrate, a liquid alloy thermal interface material (TIM) on the interposer module, a seal ring surrounding the liquid alloy TIM, and a package lid on the liquid alloy TIM and seal ring, wherein the seal ring, interposer module and package lid seal the liquid alloy TIM.

A package assembly includes an interposer module on a package substrate, a liquid alloy thermal interface material (TIM) on the interposer module, a seal ring surrounding the liquid alloy TIM, and a package lid on the liquid alloy TIM and seal ring, wherein the seal ring, interposer module and package lid seal the liquid alloy TIM.

A semiconductor device includes a substrate, a package structure, a thermal interface material (TIM) layer, and a lid structure. The package structure is disposed on the substrate. The TIM layer is disposed on the package structure. The TIM layer includes a liquid state metal material. The lid structure is disposed on the substrate and the TIM layer. The lid structure includes a trench facing the package structure. At least a portion of the TIM layer is located in the trench.