A semiconductor package includes a substrate, a package structure, a lid structure, and a thermal spreader layer. The package structure is disposed on the substrate, wherein the package structure includes a plurality of device dies and a filling material filling a gap between adjacent two of the plurality of device dies. The lid structure is disposed over substrate and covering the package structure. The thermal spreader layer is disposed between the lid structure and the package structure, wherein the thermal spreader layer has a profile that is discontinuous in thickness at a gap region corresponding to the gap.

A semiconductor package includes a substrate, a package structure, a lid structure, and a thermal spreader layer. The package structure is disposed on the substrate, wherein the package structure includes a plurality of device dies and a filling material filling a gap between adjacent two of the plurality of device dies. The lid structure is disposed over substrate and covering the package structure. The thermal spreader layer is disposed between the lid structure and the package structure, wherein the thermal spreader layer has a profile that is discontinuous in thickness at a gap region corresponding to the gap.

Embodiments of the present disclosure are directed to a leadframe package with recesses formed in outer surface of the leads. The recesses are filled with a filler material, such as solder. The filler material in the recesses provides a wetable surface for filler material, such as solder, to adhere to during mounting of the package to another device, such as a printed circuit board (PCB). This enables strong solder joints between the leads of the package and the PCB. It also enables improved visual inspection of the solder joints after the package has been mounted.

Embodiments of the present disclosure are directed to a leadframe package with recesses formed in outer surface of the leads. The recesses are filled with a filler material, such as solder. The filler material in the recesses provides a wetable surface for filler material, such as solder, to adhere to during mounting of the package to another device, such as a printed circuit board (PCB). This enables strong solder joints between the leads of the package and the PCB. It also enables improved visual inspection of the solder joints after the package has been mounted.

An electronic element mounting substrate according to the present disclosure includes a base body having a recessed portion including a mounting region on which an electronic element is mounted and a cutout section located on an outer periphery of the base body in a plane perspective, and a channel having an inner end portion located on an inner wall of the base body and an outer end portion located on the outer periphery of the base body. The inner end portion of the channel is open to the recessed portion, and the outer end portion of the channel is continuous with the cutout section.

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

A method is disclosed for producing a power semiconductor module that includes a substrate, at least one semiconductor body, a connecting element and a contact element. The method includes: arranging the substrate in a housing having walls; at least partly filling a capacity formed by the walls of the housing and the substrate with an encapsulation material; hardening the encapsulation material to form a hard encapsulation; and closing the housing, wherein the contact element extends from the connecting element through an interior of the housing and through an opening in a cover of the housing to an outside of the housing in a direction perpendicular to a first surface of a first metallization layer of the substrate.

A structure includes a first sub-structure and a second sub-structure coupled with the first sub-structure and being a composite including filler particles in a matrix. A surface of the first sub-structure has a surface profile with first elevations and first recesses configured to enable at least part of the filler particles to at least partially enter the first recesses to thereby form an interlayer including the first elevations of the first sub-structure and filler particles in the matrix of the second sub-structure.

A structure includes a first sub-structure and a second sub-structure coupled with the first sub-structure and being a composite including filler particles in a matrix. A surface of the first sub-structure has a surface profile with first elevations and first recesses configured to enable at least part of the filler particles to at least partially enter the first recesses to thereby form an interlayer including the first elevations of the first sub-structure and filler particles in the matrix of the second sub-structure.