To suppress a temperature rise of a chip accompanying a production of large output by a power converter, and to reduce a size of the power converter. A power semiconductor device includes: a first power semiconductor element to configure an upper arm of an inverter circuit; a second power semiconductor element to configure a lower arm of the inverter circuit; a first lead frame to transmit power to the first power semiconductor element; a second lead frame to transmit power to the second power semiconductor element; a first gate lead frame to transmit a control signal to the first power semiconductor element; and a sealing member to seal the first power semiconductor element, the second power semiconductor element, the first lead frame, the second lead frame, and the first gate lead frame. In the power semiconductor device, a through-hole is formed in the sealing member, and a part of the first gate lead frame and a part of the second lead frame are exposed to an inner peripheral surface of the through-hole.

To suppress a temperature rise of a chip accompanying a production of large output by a power converter, and to reduce a size of the power converter. A power semiconductor device includes: a first power semiconductor element to configure an upper arm of an inverter circuit; a second power semiconductor element to configure a lower arm of the inverter circuit; a first lead frame to transmit power to the first power semiconductor element; a second lead frame to transmit power to the second power semiconductor element; a first gate lead frame to transmit a control signal to the first power semiconductor element; and a sealing member to seal the first power semiconductor element, the second power semiconductor element, the first lead frame, the second lead frame, and the first gate lead frame. In the power semiconductor device, a through-hole is formed in the sealing member, and a part of the first gate lead frame and a part of the second lead frame are exposed to an inner peripheral surface of the through-hole.

A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate having a removable tape formed on the supporting plate, placing a plurality of chips on the removable tape, applying an adhesive layer on a back surface of each of the chips, providing a conductive cover for covering all chips and isolating the chips from each other by a plurality of partitions, injecting a molding compound into an inside of the conductive cover and curing the molding compound for forming an encapsulation, separating the encapsulation from the supporting plate, forming a connection layer on an active surface of each of the chips to establish electrical connections, and performing a cutting process to divide the encapsulation into a plurality of the package structures.

A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate having a removable tape formed on the supporting plate, placing a plurality of chips on the removable tape, applying an adhesive layer on a back surface of each of the chips, providing a conductive cover for covering all chips and isolating the chips from each other by a plurality of partitions, injecting a molding compound into an inside of the conductive cover and curing the molding compound for forming an encapsulation, separating the encapsulation from the supporting plate, forming a connection layer on an active surface of each of the chips to establish electrical connections, and performing a cutting process to divide the encapsulation into a plurality of the package structures.

There are provided a semiconductor module capable of preventing the adhesion of an epoxy resin to a terminal to which at least one of a high current and a high voltage is supplied and a method for manufacturing a semiconductor module. A semiconductor module includes: a case having an inner wall defining a casting region and a peripheral edge portion arranged outside the inner wall; an intermediate terminal arranged in along side portion of a peripheral edge portion and having a fastening surface to which a cable is fastened; a structure arranged in a long side portion of the inner wall to be adjacent to the long side portion where the intermediate terminal is arranged and higher than the fastening surface; and a sealing section formed of an epoxy resin, having weld lines formed close to the side of the structure on a surface, and cast into a casting region to seal transistors.

A filler material for an organic electroluminescent element, formed of a resin composition being liquid at 25° C., and containing a hydrocarbon polymer having a number average molecular weight of 300 or more and less than 32,000 and an organometallic compound represented by M-L.sub.n (wherein, M represents a metal atom; L represents an organic group having 9 or more carbon atoms and 1 or more oxygen atoms, and all of L represent the same organic group; and n represents the valence of a metal atom M), wherein a contact angle to silicon nitride is 10 to 40 degrees, and an amount of outgassing other than moisture upon heating at 85° C. for 1 hour is 500 ppm or less in terms of a toluene equivalent, and a method of sealing an organic electroluminescent element using the same.

A package on package (PoP) device includes a first package, a thermal interface material, and a second package coupled to the first package. The first package includes a first integrated device and a first encapsulation layer that at least partially encapsulates the first integrated device, where the first encapsulation layer includes a first cavity located laterally with respect to the first integrated device. The thermal interface material (TIM) is coupled to the first integrated device such that the thermal interface material (TIM) is formed between the first integrated device and the second package. The thermal interface material (TIM) is formed in the first cavity of the first encapsulation layer.

A stiffener, an IC package and methods of fabrication of an IC package including a removable stiffener are shown. A removable stiffener for use with an integrated circuit (IC), including a plurality of adhesive portions disposed between a surface of the stiffener and a surface of a substrate of the IC is shown. Such a removable stiffener including at least one removal tab is shown. An IC package including a removable stiffener including a plurality of adhesive portions disposed between a surface of the stiffener and a surface of a substrate of the IC is shown. Methods of fabrication of an IC package including a removable stiffener are shown.

A power semiconductor module arrangement comprises a substrate comprising a dielectric insulation layer, and a first metallization layer attached to the dielectric insulation layer, at least one semiconductor body mounted on the first metallization layer, and a first layer comprising an encapsulant, the first layer being arranged on the substrate and covering the first metallization layer the at least one semiconductor body, wherein the first layer is configured to release liquid or oil at temperatures exceeding a defined threshold temperature.

A power semiconductor module arrangement comprises a substrate comprising a dielectric insulation layer, and a first metallization layer attached to the dielectric insulation layer, at least one semiconductor body mounted on the first metallization layer, and a first layer comprising an encapsulant, the first layer being arranged on the substrate and covering the first metallization layer the at least one semiconductor body, wherein the first layer is configured to release liquid or oil at temperatures exceeding a defined threshold temperature.