Patent classifications
H01L21/54
Leadframe package with pre-applied filler material
Embodiments of the present disclosure are directed to a leadframe package with recesses formed in outer surface of the leads. The recesses are filled with a filler material, such as solder. The filler material in the recesses provides a wetable surface for filler material, such as solder, to adhere to during mounting of the package to another device, such as a printed circuit board (PCB). This enables strong solder joints between the leads of the package and the PCB. It also enables improved visual inspection of the solder joints after the package has been mounted.
Power module and method for fabricating the same, and power conversion device
A power module which inhibits disjoin between a sealing resin and an adhesive. The power module includes: an insulative substrate having a semiconductor element mounted on the top surface; a base plate joined to the rear surface of the insulative substrate; a case member with the base plate, that surrounds the insulative substrate, the case member having a bottom surface whose inner periphery portion side being in contact with a top surface of the base plate, the bottom surface being provided with an angled surface whose distance to the top surface of the base plate increases toward an outer periphery side of the base plate; an adhesive member filled between the base plate and the angled surface to adhere the base plate and the case member; and a filling member filled in a region bounded by the base plate and the case member.
METHODS OF MANUFACTURING STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS
Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.
METHODS OF MANUFACTURING STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS
Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.
CRACK IDENTIFICATION IN IC CHIP PACKAGE USING ENCAPSULATED LIQUID PENETRANT CONTRAST AGENT
A packaging fill material for electrical packaging includes a base material, and a plurality of frangible capsules distributed in the base material. Each frangible capsule includes a liquid penetrant contrast agent therein having a different radiopacity than the base material. In response to a crack forming in the packaging fill material, at least one of the plurality of frangible capsules opens, releasing the liquid penetrant contrast agent into the crack. Cracks can be more readily identified in an IC package including the packaging fill material. The liquid penetrant contrast agent may have a radiopacity that is higher than the base material. Inspection can be carried out using electromagnetic analysis using visual inspection or digital analysis of the results to more easily identify cracks.
CRACK IDENTIFICATION IN IC CHIP PACKAGE USING ENCAPSULATED LIQUID PENETRANT CONTRAST AGENT
A packaging fill material for electrical packaging includes a base material, and a plurality of frangible capsules distributed in the base material. Each frangible capsule includes a liquid penetrant contrast agent therein having a different radiopacity than the base material. In response to a crack forming in the packaging fill material, at least one of the plurality of frangible capsules opens, releasing the liquid penetrant contrast agent into the crack. Cracks can be more readily identified in an IC package including the packaging fill material. The liquid penetrant contrast agent may have a radiopacity that is higher than the base material. Inspection can be carried out using electromagnetic analysis using visual inspection or digital analysis of the results to more easily identify cracks.
EMBEDDED HEAT SLUG IN A SUBSTRATE
A substrate includes a heat slug that is disposed in a cavity in the substrate. An engineered filler material is disposed in the cavity over, under, and/or around the heat slug. The engineered filler material is a thermally conductive particle material having a composition that can be adjusted based on a desired coefficient of thermal expansion. An electronic device can be attached to the substrate over the heat slug and the engineered filler material. The heat slug and the engineered filler material provide, or are part of, a heat transfer dissipation path for the electronic device.
EMBEDDED HEAT SLUG IN A SUBSTRATE
A substrate includes a heat slug that is disposed in a cavity in the substrate. An engineered filler material is disposed in the cavity over, under, and/or around the heat slug. The engineered filler material is a thermally conductive particle material having a composition that can be adjusted based on a desired coefficient of thermal expansion. An electronic device can be attached to the substrate over the heat slug and the engineered filler material. The heat slug and the engineered filler material provide, or are part of, a heat transfer dissipation path for the electronic device.
Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.
Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.