Patent classifications
H01L21/56
CARRIER SUBSTRATES FOR SEMICONDUCTOR PROCESSING
A carrier substrate includes a base layer having a first surface, and having a second surface that is parallel to and opposite of the first surface. The carrier substrate further includes a glass layer bonded to the first surface of the base layer. The carrier substrate has a Young's modulus greater than or equal to 150 GPa. A carrier substrate includes a polycrystalline ceramic and has a Young's modulus greater than or equal to 150 GPa. The carrier substrate has a coefficient of thermal expansion of greater than or equal to 20×10.sup.−7/° C. to less than or equal to 120×10.sup.−7/° C. over a range from 25° C. to 500° C.
LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE LIGHT EMITTING DEVICE
A method of manufacturing a light emitting device includes: providing a substantially flat plate-shaped base member which in plan view includes at least one first portion having an upper surface, and a second portion surrounding the at least one first portion and having inner lateral surfaces; mounting at least one light emitting element on the at least one first portion; shifting a relative positional relationship between the at least one first portion and the second portion in an upper-lower direction to form at least one recess defined by an upper surface of the at least one first portion that serves as a bottom surface of the at least one recess and at least portions of the inner lateral surfaces of the second portion that serve as lateral surfaces of the at least one recess; and bonding the at least one first portion and the second portion with each other.
PACKAGE ASSEMBLY
In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.
Electronic Components with Integral Lead Frame and Wires
An electronic component includes one or more circuits having electrical connections coupled therewith. The electrical connections include a lead frame as well as electrical wires coupling the circuit or circuits to respective portions of the lead frame. The electrical wires may be formed as one piece with the respective portion of the lead frame without joints therebetween, e.g., by 3D printing.
Chip-On-Wafer Package and Method of Forming Same
A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A first conductive via is formed, extending from a first surface of the substrate, where the first surface is opposite the second redistribution structure, the first conductive via contacting a first conductive element in the second redistribution structure. Forming the first conductive via includes patterning an opening in the substrate, extending the opening to expose the first conductive element, where extending the opening includes using a portion of a second conductive element in the first redistribution structure as an etch mask, and filling the opening with a conductive material.
Chip-On-Wafer Package and Method of Forming Same
A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A first conductive via is formed, extending from a first surface of the substrate, where the first surface is opposite the second redistribution structure, the first conductive via contacting a first conductive element in the second redistribution structure. Forming the first conductive via includes patterning an opening in the substrate, extending the opening to expose the first conductive element, where extending the opening includes using a portion of a second conductive element in the first redistribution structure as an etch mask, and filling the opening with a conductive material.
Semiconductor device and method of forming micro interconnect structures
A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.
Wafer level package utilizing molded interposer
Semiconductor packages may include a molded interposer and semiconductor dice mounted on the molded interposer. The molded interposer may include two redistribution layer structures on opposite sides of a molding compound. Electrically conductive vias may connect the RDL structures through the molding compound, and passive devices may be embedded in the molding compound and electrically connected to one of the RDL structures. Each of the semiconductor dice may be electrically connected to, and have a footprint covering, a corresponding one of the passive devices to form a face-to-face connection between each of the semiconductor dice and the corresponding one of the passive devices.
Package structure and method for manufacturing the same
A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts.
Manufacturing method of mounting structure, and sheet therefor
A manufacturing method of a mounting structure includes: a step of preparing a mounting member including a first circuit member and a plurality of second circuit members placed on the first circuit member; a disposing step of disposing a thermosetting sheet and a thermoplastic sheet on the mounting member, with the thermosetting sheet interposed between the thermoplastic sheet and the first circuit member; a first sealing step of pressing a stack of the thermosetting sheet and the thermoplastic sheet against the first circuit member, and heating the stack, to seal the second circuit members and to cure the thermosetting sheet into a cured layer; and a removal step of removing the thermoplastic sheet from the cured layer. At least one of the second circuit members is a hollow member having a space from the first circuit member, and in the first sealing step, the second circuit members are sealed so as to maintain the space.