Patent classifications
H01L21/56
Sintering method using a sacrificial layer on the backside metallization of a semiconductor die
An electronic device comprises a semiconductor die, a layer stack disposed on the semiconductor die and comprising one or more functional layers, wherein the layer stack comprises a protection layer which is an outermost functional layer of the layer stack, and a sacrificial layer disposed on the protection layer, wherein the sacrificial layer comprises a material which decomposes or becomes volatile at a temperature between 100° and 400° C.
Liquid compression molding encapsulants
Thermosetting resin compositions useful for liquid compression molding encapsulation of a reconfigured wafer are provided. The so-encapsulated molded wafer offers improved resistance to warpage, compared to reconfigured wafers encapsulated with known encapsulation materials.
Semiconductor package with redistribution structure and manufacturing method thereof
A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
Semiconductor package with redistribution structure and manufacturing method thereof
A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
Method for producing semiconductor device and intermediate for semiconductor device
This method for producing a semiconductor device comprises: a first step wherein a plurality of semiconductor chips are affixed onto a supporting substrate such that circuit surfaces of the semiconductor chips face the supporting substrate; a second step wherein a plurality of sealed layers are formed at intervals by applying the sealing resin onto the semiconductor chips by three-dimensional modeling method, each sealed layer containing one or more semiconductor chips embedded in a sealing resin; a third step wherein the sealed layers are cured or solidified; and a fourth step wherein sealed bodies are obtained by separating the cured or solidified sealed layers from the supporting substrate.
Method for producing semiconductor device and intermediate for semiconductor device
This method for producing a semiconductor device comprises: a first step wherein a plurality of semiconductor chips are affixed onto a supporting substrate such that circuit surfaces of the semiconductor chips face the supporting substrate; a second step wherein a plurality of sealed layers are formed at intervals by applying the sealing resin onto the semiconductor chips by three-dimensional modeling method, each sealed layer containing one or more semiconductor chips embedded in a sealing resin; a third step wherein the sealed layers are cured or solidified; and a fourth step wherein sealed bodies are obtained by separating the cured or solidified sealed layers from the supporting substrate.
Serializer-deserializer die for high speed signal interconnect
In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.
Serializer-deserializer die for high speed signal interconnect
In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.
Staggered die stacking across heterogeneous modules
An electronic package can include a substrate, a first die and a second die. The first die can include a first thickness and the second die can include a second thickness. The first and second dies can be coupled to the substrate. A mold can be disposed on the substrate and cover the first die and the second die. The mold can include a planar upper surface. A first via, having a first length, can be extended between the first die and the planar upper surface. A second via, having a second length, can be extended between the second die and the planar upper surface. In some examples, a third die can be communicatively coupled to the first die using the first via and the second die using the second via.
Staggered die stacking across heterogeneous modules
An electronic package can include a substrate, a first die and a second die. The first die can include a first thickness and the second die can include a second thickness. The first and second dies can be coupled to the substrate. A mold can be disposed on the substrate and cover the first die and the second die. The mold can include a planar upper surface. A first via, having a first length, can be extended between the first die and the planar upper surface. A second via, having a second length, can be extended between the second die and the planar upper surface. In some examples, a third die can be communicatively coupled to the first die using the first via and the second die using the second via.