A method for making a semiconductor structure includes forming a first fin and a second fin over a substrate. The method includes forming one or more work function layers over the first and second fins. The method includes forming a nitride-based metal film over the one or more work function layers. The method includes covering the first fin with a patternable layer. The method includes removing a second portion of the nitride-based metal film from the second fin, while leaving a first portion of the nitride-based metal film over the first fin substantially intact.

A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.

An electronic device includes a multilevel package substrate with first, second, third, and fourth levels, a semiconductor die mounted to the first level, and a conductor backed coplanar waveguide transmission line feed with an interconnect and a conductor, the interconnect including coplanar first, second, and third conductive lines extending in the first level along a first direction from respective ends to an antenna, the second and third conductive lines spaced apart from opposite sides of the first conductive line along an orthogonal second direction, and the conductor extending in the third level under the interconnect and under the antenna.

A semiconductor chip, a semiconductor package including the same, and a method of fabricating the same, the semiconductor chip including a substrate that includes a device region and an edge region; a device layer and a wiring layer that are sequentially stacked on the substrate; a subsidiary pattern on the wiring layer on the edge region; a first capping layer that covers a sidewall of the subsidiary pattern, a top surface of the wiring layer, and a sidewall of the wiring layer, the first capping layer including an upper outer sidewall and a lower outer sidewall, the lower outer sidewall being offset from the upper outer sidewall; and a buried dielectric pattern in contact with the lower outer sidewall of the first capping layer and spaced apart from the upper outer sidewall of the first capping layer.

An electronic circuit device according to the present invention includes a base substrate including a wiring layer having a connection part, at least one electronic circuit element, and a re-distribution layer including a photosensitive resin layer, the photosensitive resin layer enclosing a surface on which a connection part of the electronic circuit element is formed and a side surface of the electronic circuit element and embedding a first wiring photo via, a second wiring photo via and a wiring, the first wiring photo via directly connected to the connection part of the electronic circuit element, the second wiring photo via arranged at the outer periphery of the electronic circuit element and directly connected to a connection part of the wiring layer, the wiring electrically connected to the first wiring photo via and the second wiring photo via on a same surface.

A semiconductor package includes a first semiconductor chip including a first surface and a second surface, and including a first active layer on a portion adjacent to the first surface; a first redistribution structure on the first surface of the first semiconductor chip, wherein the first redistribution structure includes a first area and a second area next to the first area; a second semiconductor chip mounted in the first area of the first redistribution structure, including a third surface, which faces the first surface, and a fourth surface, and including a second active layer on a portion adjacent to the third surface; a conductive post mounted in the second area of the first redistribution structure; a molding layer at least partially surrounding the second semiconductor chip and the conductive post on the first redistribution structure; and a second redistribution structure disposed on the molding layer and connected to the conductive post.

A semiconductor structure includes a molding, a device in the molding, and a RDL over the device and the molding. The RDL includes a first portion directly over a surface of the molding, and a second portion directly over a surface of the device. A bottom surface of the first portion is in contact with the surface of the molding, and a bottom surface of the second portion is in contact with the surface of the device. The bottom surface of the first portion of the RDL and the bottom surface of the second portion of the RDL are at different levels and misaligned from each other. A thickness of the first portion is greater than a thickness of the second portion.

A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

In one example, a semiconductor device can comprise (a) an electronic device comprising a device top side, a device bottom side opposite the device top side, and a device sidewall between the device top side and the device bottom side, (b) a first conductor comprising, a first conductor side section on the device sidewall, a first conductor top section on the device top side and coupled to the first conductor side section, and a first conductor bottom section coupled to the first conductor side section, and (c) a protective material covering the first conductor and the electronic device. A lower surface of the first conductor top section can be higher than the device top side, and an upper surface of the first conductor bottom section can be lower than the device top side. Other examples and related methods are also disclosed herein.

In one example, a semiconductor device can comprise (a) an electronic device comprising a device top side, a device bottom side opposite the device top side, and a device sidewall between the device top side and the device bottom side, (b) a first conductor comprising, a first conductor side section on the device sidewall, a first conductor top section on the device top side and coupled to the first conductor side section, and a first conductor bottom section coupled to the first conductor side section, and (c) a protective material covering the first conductor and the electronic device. A lower surface of the first conductor top section can be higher than the device top side, and an upper surface of the first conductor bottom section can be lower than the device top side. Other examples and related methods are also disclosed herein.