Patent classifications
H01L21/67121
Apparatus and mechanisms for reducing warpage and increasing surface mount technology yields in high performance integrated circuit packages
A stiffener apparatus for reducing warpage of an integrated circuit package during heating and cooling are provided. The stiffener apparatus includes an IC substrate configured to receive an IC die on a top side of the IC substrate. The stiffener apparatus includes a primary stiffener ring adhered to the top side of the IC substrate and defining an opening in a region of the IC die such that the primary stiffener ring surrounds the region of the IC die. The primary stiffener ring defines a plurality of grooves. The stiffener apparatus includes a secondary stiffener ring having a plurality of catches configured to engage with the plurality of grooves to removably attach the secondary stiffener ring to the primary stiffener ring on a side of the primary stiffener ring opposite the IC substrate. A method of using a stiffener apparatus during a manufacturing operation is also provided.
Diodes offering asymmetric stability during fluidic assembly
Embodiments are related to systems and methods for fluidic assembly, and more particularly to systems and methods for assuring deposition of elements in relation to a substrate.
BOARD-LEVEL ARCHITECTURE, METHOD FOR MANUFACTURING BOARD-LEVEL ARCHITECTURE, AND MOBILE TERMINAL
A board-level architecture is provided. The board-level architecture includes: a first circuit board, a system-in-a-package module, at least one conductive terminal, and at least one first component. The system-in-a-package module is fastened on an upper surface of the first circuit board. The conductive terminal is located between a lower surface of the system-in-a-package module and the upper surface of the first circuit board, and the conductive terminal is separately electrically connected to the system-in-a-package module and the first circuit board. The first component is fastened on the upper surface of the first circuit board, and the first component is located in a region between the lower surface of the system-in-a-package module and the upper surface of the first circuit board.
Packaged semiconductor device having patterned conductance dual-material nanoparticle adhesion layer
Described examples include a substrate made of a first material and having a surface. First and second nozzles respectively dispense a first solvent paste including electrically conductive nanoparticles and a second solvent paste including non-conductive nanoparticles, while moving over the surface of the substrate. The first and second nozzles additively deposit a uniform layer including sequential and contiguous zones, alternating between the first solvent paste and the second solvent paste. Energy is applied to sinter together the nanoparticles and diffuse the nanoparticles into the substrate. The sintered nanoparticles form a layer composed of an alternating sequence of electrically conductive zones contiguous with electrically non-conductive zones.
PACKAGE SUBSTRATE PROCESSING METHOD
A package substrate processing method for processing a package substrate having a division line, an electrode being formed on the division line includes a cutting step of cutting the package substrate along the division line by using a cutting blade and a burr removing step of removing burrs produced from the electrode in the cutting step by spraying a fluid to the package substrate along the division line after performing the cutting step. The cutting step includes a step of supplying a cutting liquid containing an organic acid and an oxidizing agent to a cutting area where the package substrate is to be cut by the cutting blade.
FLIP CHIP BONDING DEVICE AND BONDING METHOD
A flip-chip bonding device and method are disclosed. The bonding device includes: a supply unit (10) for separating a flip-chip (200) from a carrier (100) and providing the flip-chip (200), the supply unit (10) including flipping device (11); a transfer unit (20) for receiving the flip-chip (200) from the flipping device (11); a position adjustment unit (30) for adjusting the positions of flip-chips (200) on the transfer unit (20); a bonding unit (40) for bonding the flip-chips (200) on the transfer unit (20) onto a substrate (400); a transportation unit (50) for transporting the transfer unit (20); and a control unit (60) for controlling the movement of the preceding units. The transfer unit (20) is capable of receiving multiple flip-chips (200) and allows the flip-chips (200) to be bonded simultaneously. This can result in savings in bonding time and an improvement in throughput. Moreover, during the transportation of the transfer unit (20), the positions of the flip-chips (200) thereon can be adjusted by the position adjustment unit (30), thereby ensuring high positional accuracy of the flip-chips (200) in the subsequent bonding step. As a result, a high-accuracy bonding can be achieved.
APPARATUS AND METHOD FOR SECURING COMPONENTS OF AN INTEGRATED CIRCUIT
Systems and methods of securing an integrated circuit assembly includes: arranging a plurality of securing elements within a plurality of orifices fabricated within one or more layer components of a plurality of layer components of an integrated circuit assembly; applying a mechanical compression load against the integrated circuit assembly that uniformly compresses together the plurality of layer components of the integrated circuit assembly; after applying the mechanical compression load to the integrated circuit assembly, fastening the plurality of securing elements while the integrated circuit assembly is in a compressed state based on the mechanical compression load; and terminating the application of the mechanical compression load against the integrated circuit assembly based on the fastening of the plurality of securing elements.
DEVICE AND METHODS FOR THE TRANSFER OF CHIPS FROM A SOURCE SUBSTRATE ONTO A DESTINATION SUBSTRATE
A device for the transfer of chips from a source substrate onto a destination substrate, including: a source substrate having a lower surface and an upper surface; and a plurality of elementary chips arranged on the upper surface of the source substrate, wherein each elementary chip is suspended above the source substrate by at least one breakable mechanical fastener, said at least one breakable mechanical fastener having a lower surface fastened to the upper surface of the source substrate and an upper surface fastened to the lower surface of the chip.
Method for dividing substrate along division lines using abrasive member having projection for cutting substrate
There is provided a processing method for a package substrate having a plurality of division lines formed on the front side. The processing method includes the steps of holding the back side of the package substrate by using a holding tape and fully cutting the package substrate along the division lines to such a depth corresponding to the middle of the thickness of the holding tape by using a profile grinding tool, thereby dividing the package substrate into individual semiconductor packages. The profile grinding tool has a plurality of projections for cutting the package substrate respectively along the plural division lines. Each projection has an inclined side surface.
SYSTEM FOR COATING METHOD
The present disclosure is directed to a coating module including: a coating stage and a plurality of vertical guides configured to perpendicularly extend from the coating stage; a vertical movement mechanism configured to lower a framed panel along the plurality of vertical guides onto the coating stage; an optical alignment tool configured to provide feedback on a lateral alignment between an edge of the coating stage and the framed panel; and a dispensing unit configured to coat a surface of the panel.