An apparatus for cleaning a package device is provided. The apparatus includes a package device loader; a package device unloader; a first cleaning area disposed between the package device loader and the package device unloader; and a conveyor. The conveyor includes a frame extending from the package device loader to the package device unloader and through the first cleaning area; and a belt wrapping the frame, wherein the belt includes a movable upper surface between the package device loader and the package device unloader, wherein the movable upper surface is configured to move relative to and over the frame, and a first distance between the movable upper surface and the frame in the first cleaning area increases in a direction from the package device loader to the package device unloader.

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method comprises forming a plurality of semiconductor devices over a central region of a semiconductor wafer. The semiconductor wafer comprises a peripheral region laterally surrounding the central region and a circumferential edge disposed within the peripheral region. The semiconductor wafer comprises a notch disposed along the circumferential edge. Forming a stack of inter-level dielectric (ILD) layers over the semiconductor devices and laterally within the central region. Forming a bonding support structure over the peripheral region such that the bonding support structure comprises a bonding structure notch disposed along a circumferential edge of the bonding support structure. Forming the bonding support structure includes disposing the semiconductor wafer over a lower plasma exclusion zone (PEZ) ring that comprises a PEZ ring notch disposed along a circumferential edge of the lower PEZ ring.

A bonding apparatus configured to bond a first substrate and a second substrate includes a first holder configured to hold the first substrate; a second holder configured to hold the second substrate; a first imaging device provided at the first holder and configured to image the second substrate held by the second holder; a first light irradiating device provided at the first holder and configured to irradiate light to the second substrate when the second substrate is imaged; a second imaging device provided at the second holder and configured to image the first substrate held by the first holder; and a second light irradiating device provided at the second holder and configured to irradiate light to the first substrate when the first substrate is imaged. Each of the first light irradiating device and the second light irradiating device is connected to a first light source configured to irradiate white light.

A method includes determining an alignment error between a discrete component of a discrete component assembly mounted in a laser-assisted transfer system and a target position on a target substrate, the discrete component assembly including the discrete component adhered to a support by a dynamic release layer; based on the alignment error, determining a beam offset characteristic; and providing a signal indicative of the beam offset characteristic to an optical element of the laser-assisted transfer system, the optical element being configured to adjust a position of a beam pattern relative to the discrete component according to the beam offset characteristic.

Methods and apparatus for bonding chiplets to substrates are provided herein. In some embodiments, a multi-chamber processing tool for processing substrates, includes: a first equipment front end module (EFEM) having one or more loadports for receiving one or more types of substrates, a second EFEM having one or more loadports; and a plurality of atmospheric modular mainframes (AMMs) coupled to each other and having a first AMM coupled to the first EFEM and a last AMM coupled to the second EFEM, wherein each of the plurality of AMMs include a transfer chamber and one or more process chambers coupled to the transfer chamber, wherein the transfer chamber includes a buffer, and wherein the transfer chamber includes a transfer robot, the one or more process chambers, and a buffer disposed in an adjacent AMM of the plurality of AMMs.

The technology of this disclosure relates to a chip packaging apparatus. The chip packaging apparatus includes a first differential pin pair, a first pin, and a second pin. The first differential pin pair includes a first differential signal pin and a second differential signal pin. In addition, the first pin and the second pin are both located between the first differential signal pin and the second differential signal pin, and the first pin and the second pin are differential signal pins (or both are power pins). The first pin is adjacent to the first differential signal pin and the second differential signal pin. The second pin is adjacent to the first differential signal pin and the second differential signal pin. The first pin and the second pin are respectively located on two sides of a first imaginary straight line connecting the first differential signal pin to the second differential signal pin.

The present disclosure provides a mothed of method of manufacturing a semiconductor device. The method includes steps of forming a dielectric layer on a substrate; etching the dielectric layer to create a plurality of openings in the dielectric layer; applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer; forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed; removing the sacrificial layer to form at least one air gap in the dielectric layer; and forming a plurality of protrusions on the bases.

A package that includes a substrate having a routing region and a non-routing region along a periphery of the substrate. The non-routing region includes a plurality of vias configured as a shield. The package includes an integrated device coupled to the substrate, and an encapsulation layer located over the substrate such that the encapsulation layer encapsulates the integrated device.

A package substrate processing method for processing a package substrate having a division line, an electrode being formed on the division line includes a cutting step of cutting the package substrate along the division line by using a cutting blade and a burr removing step of removing burrs produced from the electrode in the cutting step by spraying a fluid to the package substrate along the division line after performing the cutting step. The cutting step includes a step of supplying a cutting liquid containing an organic acid and an oxidizing agent to a cutting area where the package substrate is to be cut by the cutting blade.

The present disclosure provides a semiconductor device, a method of manufacturing the semiconductor device and a mothed of method of manufacturing a semiconductor device assembly. The semiconductor device includes a substrate, a bonding dielectric disposed on the substrate, a first conductive feature disposed in the bonding dielectric, an air gap disposed in the bonding dielectric to separate a portion of a periphery of the first conductive feature from the bonding dielectric, and a second conductive feature including a base disposed in the bonding dielectric and a protrusion stacked on the base.