A plasma processing apparatus capable of achieving a uniform plasma space therein is provided. The plasma processing apparatus includes a processing vessel, a mounting table, a shield member, a shutter for an opening configured to be moved up and down, a first driving unit and a second driving unit. The processing vessel has a sidewall, and the sidewall is provided with a transfer path through which a processing target object is carried-in/carried-out. The mounting table is provided within the processing vessel. The shield member is provided along an inner surface of the sidewall to surround the mounting table and provided with an opening facing the transfer path. The first driving unit is configured to move the shutter up and down. The second driving unit is configured to move the shutter in a forward-backward direction with respect to the shield member.

Provided are an apparatus and a method for treating a substrate at a high-pressure atmosphere. The apparatus for treating the substrate includes a first body and a second body combined with each other to define a treatment space in which the substrate is treated, a sealing member interposed between the first body and the second body to seal the treatment space from an outside at a position in which the first body is in close contact with the second body, and a driving member to drive the first body or the second body such that the treatment space is open or closed. The sealing member is positioned in a sealing groove formed in the first body. The sealing member is deformed to be in close contact with the second body by pressure of the treatment space when a process is performed.

Systems and methods are described for integrated decomposition and scanning of a semiconducting wafer, where a single chamber is utilized for decomposition and scanning of the wafer of interest.

A method of real time leveling control between a superstrate and a substrate is provided. A contact force model indicating a relationship between a total contact force for planarization of a formable material between the superstrate and the substrate and a force component of the total contact force along each of a plurality peripheral axes is identified. A set point force required for performing the planarization is determined. Each force component is calculated based on the contact force model. The planarization is performed by applying each force component along a corresponding axis of the plurality of axes. The contact force model is identified based on a parallel condition between two contacting surfaces of a superstrate chuck for retaining the superstrate and a stack of the superstrate, the substrate, and formable material between the superstrate and the substrate.

The present disclosure relates to high pressure processing apparatus for semiconductor processing. The apparatus described herein include a high pressure process chamber and a containment chamber surrounding the process chamber. A high pressure fluid delivery module is in fluid communication with the high pressure process chamber and is configured to deliver a high pressure fluid to the process chamber.

A method of encapsulating an electronic component. The method includes applying a first layer of an encapsulating composition onto an electronic component from an applicator roll, the electronic component being disposed on a substrate. The applicator roll comprises an outer surface and is spaced apart from the electronic component such that a gap exists between the applicator roll and the electronic component. The gap controls the thickness of the first layer of encapsulating composition. The first layer of encapsulating composition encapsulates the electronic component on the substrate. An interface between the surface of the electronic component and the encapsulating composition being substantially free of voids.

A sealing member for use in sealing a chamber for treating a substrate, the sealing member inserted in a groove formed in the chamber, includes a bottom part, a top part opposite the bottom part, an inner part connecting a first side of the bottom part to the top part, an outer part opposite the inner part and connecting a second side of the bottom part to the top part, and a recessed portion between the top part and the outer part.

Disclosed are an underfill method and apparatus for a semiconductor package, the underfill method includes loading a substrate; charging a filler to be filled in between the substrate and a device; applying the filler to the substrate; and subjecting the applied filler to an electric field.

Provided is an assembly jig set of semiconductor module having a plurality of semiconductor chips, the assembly jig set comprising: a first outer frame jig; and a plurality of inner piece jigs positioned by the first outer frame jig and each having a sectioned shape corresponding to the first outer frame jig, wherein one of the inner piece jigs has a plurality of opening portions for positioning the semiconductor chips. A manufacturing method of a semiconductor module using an assembly jig set is provided.

A method is provided for producing a hermetically sealed housing having a semiconductor component. The method comprises introducing a housing having a housing body and a housing cover into a process chamber. The housing cover closes off a cavity of the housing body and is attached in a gas-tight manner to the housing body. At least one opening is formed in the housing. At least one semiconductor component is arranged in the cavity. The method furthermore comprises generating a vacuum in the cavity by evacuating the process chamber, and also generating a predetermined gas atmosphere in the cavity and the process chamber. The method moreover comprises applying sealing material to the at least one opening while the predetermined gas atmosphere prevails in the process chamber.