A method of forming a semiconductor device includes forming a tungsten layer over a semiconductor substrate in a first chamber, transferring the substrate over which the tungsten layer is formed from the first chamber to a second chamber without exposing into an atmosphere including oxygen, and forming a silicon nitride layer on the tungsten layer in the second chamber.

Methods disclosed herein include scanning a focus spot formed by a laser beam over either a metal layer or IC structures that include a metal and a non-metal. The focus spot is scanned over a scan path that includes scan path segments that partially overlap. The focus spot has an irradiance and a dwell time selected to locally melt the metal layer or locally melt the metal of the IC structures without melting the non-metal. This results in rapid melting and recrystallization of the metal, which decreases the resistivity of the metal and results in improved performance of the IC chips being fabricated. Also disclosed is an example laser melt system for carrying out methods disclosed herein is also disclosed.

Methods and apparatus to form fully self-aligned vias are described. First conductive lines are recessed in a first insulating layer on a substrate. A first metal film is formed in the recessed first conductive lines and pillars are formed from the first metal film. Some of the pillars are selectively removed and a second insulating layer is deposited around the remaining pillar. The remaining pillars are removed to form vias in the second insulating layer. A third insulating layer is deposited in the vias and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is etched from the filled vias to form a via opening to the first conductive line.

Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a Ni.sub.xSi.sub.1-x layer on the substrate, where x is between about 0.01 and about 0.99.

In a method of manufacturing a semiconductor memory device, a plurality of first conductive structures including a first conductive pattern and a hard mask are sequentially stacked on a substrate. A plurality of preliminary spacer structures including first spacers, sacrificial spacers and second spacers are sequentially stacked on sidewalls of the conductive structures. A plurality of pad structures are formed on the substrate between the preliminary spacer structures, and define openings exposing an upper portion of the sacrificial spacers. A first mask pattern is formed to cover surfaces of the pad structures, and expose the upper portion of the sacrificial spacers. The sacrificial spacers are removed to form first spacer structures having respective air spacers, and the first spacer structures include the first spacers, the air spacers and the second spacers sequentially stacked on the sidewalls of the conductive structures.

A method of forming a semiconductor device includes forming a tungsten layer over a semiconductor substrate in a first chamber, transferring the substrate over which the tungsten layer is formed from the first chamber to a second chamber without exposing into an atmosphere including oxygen, and forming a silicon nitride layer on the tungsten layer in the second chamber.

Disclosed is a COB die bonding and wire bonding system and method. The system comprises a controller, a forward die bonder, a reverse die bonder and a conveyor belt, the controller being connected with the forward die bonder and the reverse die bonder respectively, and the forward die bonder is associated with the reverse die bonder by the conveyor belt. The system and method can realize the combination of the forward and reverse bonding when using the forward die bonder and the reverse die bonder to fix the chips, thus the amount of gold wire used for connecting chips on a substrate is minimized. The COB die bonding and wire bonding system and method can be widely used in the field of electronics.

An apparatus and method for providing an artificial standoff to the bottom of leads on a QFN device sufficient to provide a gap that changes the fluid dynamics of solder flow and create a unique capillary effect that drives solder up the of leads of a QFN device when it is attached to a printed wiring board (PWB).

Provided is a wire tension adjuster (60) that adjusts tension (T) applied to a wire (18) of a wire bonding apparatus (100). In the wire tension adjuster (60), in a state in which the wire (18) is gripped by a wire clamper (17), air is supplied to a wire tensioner (40) and a height position (H) of a tip (14f) of a bonding arm (14) is detected, and a flow rate (G) of the air supplied to the wire tensioner (40) is adjusted based on the height position (H) detected, thereby adjusting the tension (T) applied to the wire (18).

A soldering apparatus as a conveyance apparatus includes a substrate loading portion to load a substrate on the soldering apparatus, an intermittent feeding unit to intermittently feed the substrate loaded on the soldering apparatus, a substrate discharge portion to discharge the intermittently fed substrate to the outside of the soldering apparatus and a controller to control conveyance of the substrate. The substrate loading portion includes a first conveyance path to convey the substrate, a first sensor provided in the vicinity of a substrate loading inlet of the substrate loading portion, and a second sensor arranged in a downstream side of the first sensor along the substrate conveyance direction. The intermittent feeding unit includes a second conveyance path for conveying the substrate, and a third sensor placed in the vicinity of an upstream end of the intermittent feeding unit along the substrate conveyance direction.