A high voltage device includes: a semiconductor layer, a well, a body region, a body contact, a gate, a source, and a drain. The body cofntact is configured as an electrical contact of the body region. The body contact and the source overlap with each other to define an overlap region. The body contact has a depth from an upper surface of the semiconductor layer, wherein the depth is deeper than a depth of the source, whereby a part of the body contact is located vertically below the overlap region. A length of the overlap region in a channel direction is not shorter than a predetermined length, so as to suppress a parasitic bipolar junction transistor from being turning on when the high voltage device operates, wherein the parasitic bipolar junction transistor is formed by a part of the well, a part of the body region and a part of the source.

An integrated circuit device includes a substrate including active regions, a direct contact electrically connected to a first active region selected from the active regions, a buried contact plug electrically connected to a second active region selected from the active regions, the second active region adjacent to the first active region in a first horizontal direction, and including a conductive semiconductor layer, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction and electrically connected to the direct contact, a conductive landing pad extending toward the buried contact plug in a vertical direction, having a sidewall facing the bit line in the first horizontal direction, and including a metal, and an outer insulating spacer between the bit line and the conductive landing pad, in contact with the sidewall of the conductive landing pad, and spaced apart from the buried contact plug.

A 3D semiconductor device with a built-in-test-circuit (BIST), the device comprising: a first single-crystal substrate with a plurality of logic circuits disposed therein, wherein said first single-crystal substrate comprises a device area, wherein said plurality of logic circuits comprise at least a first interconnected array of processor logic, wherein said plurality of logic circuits comprise at least a second interconnected set of circuits comprising a first logic circuit, a second logic circuit, and a third logic circuit, wherein said second interconnected set of logic circuits further comprise switching circuits that support replacing said first logic circuit and/or said second logic circuit with said third logic circuit; and said built-in-test-circuit (BIST), wherein said first logic circuit is testable by said built-in-test-circuit (BIST), and wherein said second logic circuit is testable by said built-in-test-circuit (BIST).

A semiconductor device, includes: a substrate including active regions extending in a first direction; gate electrodes extending in a second direction, intersecting the active regions; source/drain regions disposed in regions in which the active regions are recessed; buried interconnection lines disposed in the substrate; a first lower contact plug penetrating through a portion of the substrate, and connecting at least one of the source/drain regions and at least one of the buried interconnection lines; a second lower contact plug penetrating through a portion of the substrate, and connecting at least one of the gate electrodes and at least one of the buried interconnection lines; and upper contact plugs connected to a portion of the source/drain regions and a portion of the gate electrodes, wherein upper surfaces of the first and second lower contact plugs are disposed on a level lower than a level of upper surfaces of the gate electrodes.

A method for manufacturing a semiconductor structure includes: providing a substrate; forming a gate trench in the substrate, the gate trench including a first trench and a second trench, the second trench being located above the first trench, communicating with the first trench, and having a width greater than a width of the first trench; and forming a gate word line in the gate trench.

Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.

Embodiments disclosed herein describe a semiconductor structure. The semiconductor structure may include a device region with a first source/drain (S/D) and a second S/D. The semiconductor structure may also include a buried power rail (BPR) under the device region. A critical dimension of the BPR may be larger than a distance between the first S/D and the second S/D. The semiconductor structure may also include a via-contact-to-buried power rail (VBPR) between the BPR and the S/D.

A semiconductor device is provided. The semiconductor device includes a protective liner, and a buried power rail on a first portion of the protective liner, wherein the protective liner is on opposite sides of the buried power rail. The semiconductor device further includes a source/drain on a second portion of the protective liner, wherein the source/drain is offset from the buried power rail, and a source/drain contact on the source/drain and in electrical communication with the buried power rail.

A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors) atop the third metal layer; a fourth metal layer disposed above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid, which includes the fifth metal layer; a local power distribution grid, which includes the second metal layer, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer.

A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.