According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell.

A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer disposed over the first single crystal silicon layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; and a via disposed through the first level, where the fourth metal layer provides a global power distribution, and where a typical thickness of the fourth metal layer is at least 50% greater than a typical thickness of the third metal.

A substrate includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer encapsulating the polycrystalline ceramic core, a barrier layer encapsulating the first adhesion layer, a second adhesion layer coupled to the barrier layer, and a conductive layer coupled to the second adhesion layer. The substrate also includes a bonding layer coupled to the support structure, a substantially single crystal silicon layer coupled to the bonding layer, and an epitaxial semiconductor layer coupled to the substantially single crystal silicon layer.

A semiconductor device structure includes an isolation structure disposed in a semiconductor substrate. The semiconductor device structure also includes a gate electrode and a resistor electrode disposed in the semiconductor substrate. The isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. The semiconductor device structure further includes a source/drain (S/D) region disposed in the semiconductor substrate and between the gate electrode and the isolation structure. The S/D region is electrically connected to the resistor electrode.

Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate overlying a handle substrate and an insulator layer disposed between the device substrate and the handle substrate. A gate electrode overlies the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulator layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and comprises a first isolation segment disposed laterally between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode directly overlies the first isolation segment and is electrically coupled to the contact region.

A 3D semiconductor device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where a second metal layer is disposed atop the first metal layer; a plurality of logic gates including the first metal layer and first transistors; a plurality of second transistors disposed atop the second metal layer; a plurality of third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, where the memory array includes at least four memory mini arrays, where each of the mini arrays includes at least two rows by two columns of memory cells, where each memory cell includes one of the second transistors or one of the third transistors, and where one of the second transistors is self-aligned to one of the third transistors, being processed following a same lithography step.

Structures including a vertical field-effect transistor and fabrication methods for a structure including a vertical field-effect transistor. A vertical field-effect transistor includes a source/drain region located in a section of a semiconductor layer, a first semiconductor fin projecting from the source/drain region, a second semiconductor fin projecting from the source/drain region, and a gate electrode on the section of the semiconductor layer and coupled with the first semiconductor fin and with the second semiconductor fin. The structure further includes a contact located in a trench defined in the section of the semiconductor layer between the first semiconductor fin and the second semiconductor fin. The contact is coupled with the source/drain region of the vertical field-effect transistor.

A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin including a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The semiconductor device structure further includes a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin, a first source/drain epitaxial feature in contact with the semiconductor fin, and a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer. The first inner spacer is in contact with the first source/drain epitaxial feature, and the first inner spacer comprises a first material. The semiconductor device structure further includes a first spacer in contact with the first inner spacer, and the first spacer comprises a second material different from the first material.

A method producing a nano-sized interconnect structure that electrically connects the front side of a semiconductor substrate to the back side of the substrate is provided. In one aspect, the method produces a semiconductor component such as an integrated circuit chip that includes active devices formed on the front side of the substrate, and an interconnect network such as a power delivery network on the back side of the substrate. The substrate includes a lower semiconductor layer, an intermediate layer, and an upper layer. A trench is formed through the upper layer, the material of the intermediate layer is etched from inside the trench to form a cavity at the foot of the trench, and the trench and the cavity are filled with an electrically conductive material to form a buried rail with a wide contact pad at the foot of the rail, that is, wider than the width of the rail and extending between the front and back surfaces of the intermediate layer. A nanoTSV connection is processed from the back of the substrate, the nanoTSV contacting the contact pad, to thereby form the interconnect structure.

A semiconductor device includes a first buried power rail (BPR) disposed through etch stop layers and a second BPR disposed in direct contact with the first BPR, where the first BPR has a larger critical dimension (CD) than the second BPR. A bottom surface of the first BPR directly contacts a via-to buried power rail (VBPR) contact. Source/drain contacts (CA) are disposed adjacent the VBPR contact and source/drain regions collectively defining middle-of-line (MOL) components. Back-end-of-line (BEOL) components are then constructed adjacent to the MOL components, and the MOL and BEOL components bond to a carrier wafer. The second BPR is then constructed on the carrier wafer.