A method of producing a gate cut in a semiconductor component is provided. In one aspect, an array of nano-sized semiconductor fins is processed on a semiconductor substrate. Rails may be buried in the substrate and in a layer of dielectric material that isolates neighboring fins from each other. The rails may extend in the direction of the fins and each rail may be situated between two adjacent fins. The rails may be buried power rails for enabling the formation of a power delivery network at the back of an integrated circuit chip. At the front side of the substrate, one or more gate structures are produced. The gate structures extend transversally, or perpendicularly, with respect to the fins and the rails. A gate cut is produced by forming an opening from the back side of the substrate, and removing a portion of the gate structure at the bottom of the opening, thereby creating a gate cut that is aligned to the sidewalls of the rail. In another aspect, a semiconductor component, such as an integrated circuit, includes a gate cut that is aligned to the sidewalls of a buried contact rail.

A method includes: doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface.

A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, a first metal layer (includes interconnection of first transistors), and a second metal layer, where first transistors' interconnection includes forming logic gates; a plurality of second transistors disposed atop, at least in part, of logic gates; a plurality of third transistors disposed atop, at least in part, of the second transistors; a third metal layer disposed above, at least in part, the third transistors; a global grid to distribute power and overlaying, at least in part, the third metal layer; a local grid to distribute power to the logic gates, the local grid is disposed below, at least in part, the second transistors, where the second transistors are aligned to the first transistors with less than 40 nm misalignment, where at least one of the second transistors includes a metal gate.

A method of manufacturing a semiconductor substrate according to an embodiment includes a first step of forming a groove having a bottom surface and a side surface on which scallops are formed by performing a process including isotropic etching on a main surface of a substrate, a second step of performing at least one of a hydrophilic treatment on the side surface of the groove and a degassing treatment on the groove, and a third step of removing the scallops formed on the side surface of the groove and planarizing the side surface by performing anisotropic wet etching in a state where the bottom surface of the recess is present.

A 3D semiconductor device including: a first level including a single crystal layer and plurality of first transistors; a first metal layer including interconnects between first transistors, where the interconnects between the first transistors includes forming logic gates; a second metal layer atop at least a portion of the first metal layer, second transistors which are vertically oriented, are also atop a portion of the second metal layer; where at least eight of the first transistors are connected in series forming at least a portion of a NAND logic structure, where at least one of the second transistors is at least partially directly atop of the NAND logic structure; and a third metal layer atop at least a portion of the second transistors, where the second metal layer is aligned to the first metal layer with a less than 150 nm misalignment.

A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.

A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming first alignment marks and control circuits in and on the first level, where the control circuits include first single crystal transistors, where the control circuits include at least two metal layers; forming at least one second level disposed on top of the first level; performing a first etch step within the second level; forming at least one third level disposed on top of the at least one second level; performing a second etch step within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where the first memory cells include second transistors, and where the second memory cells include third transistors.

Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well has an edge that is substantially beneath an edge of an active area of a tap to the well.

A method for processing a 3D integrated circuit, the method including: providing a first level including a first wafer, the first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; processing a second level including a second wafer, the second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; then forming a bonded structure by bonding the second level to the first level, where the bonding includes metal to metal bonding, where the bonding includes oxide to oxide bonding; and then performing a lithography process to define dice lines for the bonded structure; and etching the dice lines.

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a substrate and a seed layer on the substrate. The substrate includes a base and a composite layer encapsulating the base. The semiconductor structure also includes an epitaxial layer on the seed layer. The semiconductor structure also includes a semiconductor device on the epitaxial layer, and an interlayer dielectric layer on the epitaxial layer. The interlayer dielectric layer covers the semiconductor device. The semiconductor structure further includes a via structure that penetrates at least the composite layer of the substrate and is in contact with the base.